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* radeon: add blit function to vtblMaciej Cencora2010-01-191-0/+20
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* intel: Remove dead note_fence vtbl hook.Eric Anholt2010-01-194-10/+0
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* i965: Improve the hashing of brw_state_cache keys to include the cache_id.Eric Anholt2010-01-191-32/+54
| | | | No measurable difference on cairoperf.
* i965: Remove obsolete comment about the state atoms.Eric Anholt2010-01-191-7/+1
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* i965: Upload as many VS constants as possible through the push constants.Eric Anholt2010-01-195-12/+84
| | | | | | | The pull constants require sending out to an overworked shared unit and waiting for a response, while push constants are nicely loaded in for us at thread dispatch time. By putting things we access in every VS invocation there, ETQW performance improved by 2.5% +/- 1.6% (n=6).
* i965: Allow for variable-sized auxdata in the state cache.Eric Anholt2010-01-1917-168/+124
| | | | | | Everything has been constant-sized until now, but constant buffer handling changes will make us want some additional variable sized array.
* intel: Use the new DRI2 flush invalidate entrypoint to signal frame done.Eric Anholt2010-01-192-20/+21
| | | | | | | | | | | | | Previously for frame throttling we would wait on the first batch after a swap before emitting another swap, because we had no hook after a swap was emitted. This meant that if an app managed to squeeze everything it for a frame had into one batch, it would lock-step with the GPU. With the swapbuffers changes, we now have the entrypoint we want. This takes the WoW intro screen from 25% GPU idle and visibly jerky to 4-5% GPU idle and rather smooth. Other apps such as OpenArena have run into this problem as well.
* r100/r200/r600: fix typo in 2b1d5ea4f0250a6a7fa312ced0a7af85e909381bAlex Deucher2010-01-193-3/+3
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* r100/r200/r600: check if blitting for given format is supported earlierAlex Deucher2010-01-193-4/+105
| | | | based on Maciej's r300 patch.
* r100/r200: add blit support for ARGB4444Alex Deucher2010-01-192-0/+12
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* r60: Add relocs for CB_TILE/FRAGAlex Deucher2010-01-181-5/+24
| | | | as per 46dc6fd3ed5ef96cda53641a97bc68c3bc104a9f
* r100: add blit supportAlex Deucher2010-01-187-2/+623
| | | | Only enabled with KMS.
* r200: add blit supportAlex Deucher2010-01-186-0/+604
| | | | Only enabled with KMS.
* i965: Clean up constbuf handling by splitting reladdr/non-reladdr loads.Eric Anholt2010-01-181-46/+68
| | | | The codepaths in the function were almost entirely different.
* i965: Only set up the stack register if it's going to get used.Eric Anholt2010-01-182-6/+23
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* i965: Fix loads of non-relative-addr constants after a reladdr load.Eric Anholt2010-01-181-1/+7
| | | | Fixes piglit vp-arl-constant-array-huge-overwritten.
* r600: fix some warningsAlex Deucher2010-01-182-6/+7
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* r600: Update default state size to account for the new relocationJerome Glisse2010-01-181-1/+1
| | | | | | the new relocation for CB_COLOR0_FRAG & CB_COLOR0_TILE add 4 dwords to the default command stream. Increase the prediction default size to take this into account
* r6xx/r7xx: emit relocation for FRAG & TILE bufferJerome Glisse2010-01-181-3/+21
| | | | | | | | FRAG & TILE buffer are unused but still they need to be associated with a valid relocation so that userspace can't try to abuse them to overwritte GART and then try to write anywhere in system memory.
* r600: fix shadow_ambient shaderAndre Maasikas2010-01-181-1/+1
| | | | | | rtype enums are different, DST_REG_OUTPUT got SRC_REG_CONSTANT in some shaders and produced invalid output/hang as TEX output is temp register always set out src to SRC_REG_TEMPORARY
* radeon_compiler: include main/compiler.h for compiler portability macrosAlan Coopersmith2010-01-171-0/+2
| | | | | Signed-off-by: Alan Coopersmith <[email protected]> Reviewed-by: Corbin Simpson <[email protected]>
* r600: remove stray END_BATCH in blit codeAlex Deucher2010-01-161-1/+0
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* r600: improve blit supportAlex Deucher2010-01-152-247/+1074
| | | | | | | | | | - fill in more src/dst formats - disable depth copies for now - set proper data formats in render target regs - fill in additional default state The swizzles on some of the less used mesa formats are probably wrong.
* r600: add initial blit supportAndre Maasikas2010-01-157-323/+701
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* r600: add r600_blit.cAlex Deucher2010-01-151-0/+609
| | | | Unfinished.
* Merge branch 'master' of ssh://people.freedesktop.org/~jbarnes/mesaJesse Barnes2010-01-118-8/+43
|\ | | | | | | | | | | Conflicts due to DRI1 removal: src/mesa/drivers/dri/intel/intel_context.c src/mesa/drivers/dri/intel/intel_screen.c
| * intel/DRI2: add DRI2flushExtension support with invalidate hookKristian Høgsberg2010-01-085-17/+44
| | | | | | | | | | | | Needed to support the SwapBuffers code properly. Signed-off-by: Kristian Høgsberg <[email protected]>
| * DRI2/GLX: add INTEL_swap_event supportJesse Barnes2010-01-081-0/+3
| | | | | | | | | | | | | | Add event support for the GLX swap buffers event, along with DRI2 protocol support for generating GLX swap buffers events in the direct rendered case. Signed-off-by: Jesse Barnes <[email protected]>
| * DRI2: add SwapBuffers supportJesse Barnes2010-01-082-0/+3
| | | | | | | | | | | | | | | | | | | | Support the new DRI2 protocol request, DRI2SwapBuffers, in both direct and indirect rendering context. This request allows the display server to optimize back->front swaps (e.g. through page flipping) and allows us to more easily support other GLX features like swap interval and the OML sync extension in DRI2. Signed-off-by: Jesse Barnes <[email protected]>
* | radeon: fix prediction for r100 inline vert/elt emits.Dave Airlie2010-01-111-0/+1
| | | | | | | | | | On r100 we emit the indices inline so we need to account for that in the emission size.
* | radeon: fix bug in realloc code.Dave Airlie2010-01-111-1/+1
| | | | | | | | This bug was fixed in libdrm ages ago, port to non-kms
* | r300: minor accelerated blit fixesMaciej Cencora2010-01-091-1/+14
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* | r300: fallback on depth buffer blitsMaciej Cencora2010-01-091-3/+5
| | | | | | | | Depth buffer accelerated blits aren't implemented yet.
* | Merge branch 'mesa_7_7_branch'Brian Paul2010-01-085-42/+55
|\ \ | | | | | | | | | | | | | | | Conflicts: src/mesa/drivers/dri/i965/brw_wm_emit.c
| * | r300: Move initial declaration outside for loop.Vinson Lee2010-01-081-2/+4
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| * | meta: remove F suffix from _mesa_Ortho() paramsBrian Paul2010-01-061-3/+3
| | | | | | | | | | | | _mesa_Ortho() takes GLdoubles.
| * | meta: move destination vertex/projection setup out of _mesa_meta_GenerateMipmapBrian Paul2010-01-061-19/+21
| | | | | | | | | | | | Based on a patch submitted by Pierre Willenbrock <[email protected]>
| * | meta: set viewport and projection matrix in _mesa_meta_GenerateMipmapBrian Paul2010-01-061-0/+9
| | | | | | | | | | | | | | | | | | This fixes mipmap levels being clipped to the last viewport. Based on a patch submitted by Pierre Willenbrock <[email protected]>
| * | r600: adjust after radeon mipmap changes in 7118db8700Andre Maasikas2010-01-062-6/+5
| | | | | | | | | | | | | | | | | | R600_OUT_BATCH_RELOC doesn't really use offset so set it in TEX_RESOURCE2 + typo fix
| * | r600: float texture component orderingPierre Ossman2010-01-061-20/+20
| | | | | | | | | | | | | | | | | | | | | The ordering of texture components was backwards for the floating point textures. Signed-off-by: Pierre Ossman <[email protected]>
| * | mesa: test index bounds before array elementRoel Kluin2010-01-061-1/+1
| | | | | | | | | | | | | | | | | | | | | Check whether the index is within bounds before accessing the array. Signed-off-by: Roel Kluin <[email protected]> Signed-off-by: Brian Paul <[email protected]>
| * | i965: fix invalid assertion in emit_xpd(), againBrian Paul2010-01-061-1/+1
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* | | intel: Remove leftover symlinks from DRI1 removal.Eric Anholt2010-01-072-2/+0
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* | | i810: use ColorMask[0]Brian Paul2010-01-071-1/+1
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* | | r300/compiler: add full viewport transformation support in WPOS codegenMarek Olšák2010-01-064-6/+16
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* | | Make sure we use only signed/unsigned ints with bitfields.Michal Krol2010-01-063-13/+13
| | | | | | | | | | | | Seems to be the only way to stay fully portable.
* | | Merge remote branch 'origin/mesa_7_7_branch'José Fonseca2010-01-061-1/+1
|\| | | | | | | | | | | | | | | | | | | | Conflicts: configs/default src/gallium/auxiliary/pipebuffer/pb_buffer_fenced.c src/mesa/main/version.h
| * | i965: fix invalid assertion in emit_xpd()Brian Paul2010-01-051-1/+1
| | | | | | | | | | | | Invalid assertion found by Roel Kluin <[email protected]>
| * | tdfx: condition always evaluates to false in SetupDoubleTexEnvVoodoo3()Roel Kluin2010-01-051-1/+1
| | | | | | | | | | | | | | | | | | This can never be true. Signed-off-by: Roel Kluin <[email protected]>
* | | i965: Fix build after blind merge of mesa 7.7 by Brian.Eric Anholt2010-01-051-2/+3
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