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* i965: Access TES shader info via NIR.Kenneth Graunke2017-01-071-6/+6
* mesa: Introduce a compiler enum for tessellation spacing.Kenneth Graunke2017-01-072-15/+9
* compiler: Change shader_info->tes.vertex_order into a ccw boolean.Kenneth Graunke2017-01-071-10/+3
* drirc: Allow extension midshader for Divinity: Original Sin (EE)Kai Wasserbäch2017-01-071-0/+4
* i965/compiler: Use the new nir_opt_copy_prop_vars passJason Ekstrand2017-01-061-0/+1
* i965: Rework gl_TessLevel*[] handling to use NIR compact arrays.Kenneth Graunke2017-01-0610-364/+92
* i965: Inline store_output helper in quads workaround code.Kenneth Graunke2017-01-061-14/+10
* i965: Make unify_interfaces not spread VARYING_BIT_TESS_LEVEL_*.Kenneth Graunke2017-01-061-2/+5
* i965: Enable several GLES 3.1 extensions on HSW+Ian Romanick2017-01-061-3/+3
* i965: Always set MaxViewports and related limitsIan Romanick2017-01-061-2/+1
* i965: Properly flush in hsw_pause_transform_feedback().Kenneth Graunke2017-01-061-0/+3
* i965: Fix texturing in the vec4 TCS and GS backends.Kenneth Graunke2017-01-061-2/+12
* i965: Don't set EmitNoMainReturn.Kenneth Graunke2017-01-051-1/+0
* st/mesa/glsl: set SamplersUsed directly in gl_programTimothy Arceri2017-01-061-1/+0
* mesa: make _CurrentFragmentProgram a gl_program struct pointerTimothy Arceri2017-01-061-6/+2
* i965: stop passing gl_shader_program to the precompile and codegen functionsTimothy Arceri2017-01-0612-87/+31
* i965: make use of new is_arb_asm flagTimothy Arceri2017-01-062-13/+11
* st/mesa/glsl: add new is_arb_asm flag in gl_programTimothy Arceri2017-01-063-12/+14
* i965: pass gl_program directly to brw_compile_tes()Timothy Arceri2017-01-063-6/+4
* i965: stop passing gl_shader_program to brw_nir_setup_glsl_uniforms()Timothy Arceri2017-01-068-18/+13
* i965: pass gl_program to brw_upload_ubo_surfaces()Timothy Arceri2017-01-066-22/+20
* i965: stop passing gl_shader_program to brw_assign_common_binding_table_offse...Timothy Arceri2017-01-068-32/+13
* st/mesa/glsl/i965: move ShaderStorageBlocks to gl_programTimothy Arceri2017-01-061-1/+1
* st/mesa/glsl/i965: set num_ssbos directly in shader_infoTimothy Arceri2017-01-062-6/+9
* st/mesa/glsl/i965: move per stage UniformBlocks to gl_programTimothy Arceri2017-01-061-1/+1
* st/mesa/glsl/i965: set num_ubos directly in shader_infoTimothy Arceri2017-01-062-4/+4
* st/mesa/glsl/i965: move ImageUnits and ImageAccess fields to gl_programTimothy Arceri2017-01-067-41/+23
* i965: get InfoLog and LinkStatus via the pointer in gl_programTimothy Arceri2017-01-061-4/+4
* i965: get shared_size from shader_info rather than gl_shader_programTimothy Arceri2017-01-061-2/+2
* i965: stop depending on gl_shader_program for brw_compute_vue_map() paramsTimothy Arceri2017-01-061-1/+1
* i965: pass gl_program to the brw_*_debug_recompile() functionsTimothy Arceri2017-01-067-138/+125
* i965: Print VS output VUE map in Vulkan too.Kenneth Graunke2017-01-052-3/+5
* i965: Fix last slot calculationsKenneth Graunke2017-01-051-3/+13
* i965: add a kernel_features bitfield to intel screenIago Toral Quiroga2017-01-055-22/+59
* i965/gen7: Enable OpenGL 4.0 in Haswell when supportedIago Toral Quiroga2017-01-052-1/+4
* i965: get rid of brw->can_do_pipelined_register_writesIago Toral Quiroga2017-01-055-10/+10
* i965: Move the pipelined test for SO register access to the screenChris Wilson2017-01-054-73/+103
* i965/disasm: remove printing hstride and width in align16 DF source regionsSamuel Iglesias Gonsálvez2017-01-051-4/+1
* vec4: use DIM instruction when loading DF immediates in HSWSamuel Iglesias Gonsálvez2017-01-051-0/+9
* i965: remove unused brwInitVtbl declarationTapani Pälli2017-01-041-5/+0
* i965: remove brw_context dependency from intel_batchbuffer_init()Iago Toral Quiroga2017-01-043-28/+36
* i965: make intel_batchbuffer_free() take a batchbuffer as argumentIago Toral Quiroga2017-01-043-6/+6
* i965: make intel_batchbuffer_emit_dword() take a batchbuffer as argumentIago Toral Quiroga2017-01-042-12/+12
* i965: Make intel_bachbuffer_reloc() take a batchbuffer argumentIago Toral Quiroga2017-01-043-15/+15
* meta: Disable dithering during glGenerateMipmapChad Versace2017-01-031-0/+1
* i965: Remove perf monitor/query backendRobert Bragg2017-01-036-1597/+1
* i965/vec4: enable ARB_gpu_shader_fp64 for HaswellIago Toral Quiroga2017-01-031-0/+3
* i965/vec4: adjust spilling costs for 64-bit registers.Iago Toral Quiroga2017-01-031-2/+13
* i965/vec4: prevent spilling of DOUBLE_TO_SINGLE destinationIago Toral Quiroga2017-01-031-0/+12
* i965/vec4: avoid spilling of registers that mix 32-bit and 64-bit accessIago Toral Quiroga2017-01-031-0/+24
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