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* meta/texsubimage: tex_image is always non-null, avoid confusing codeIlia Mirkin2016-07-111-1/+1
| | | | | | | | Probably a copy-paste from mesa_meta_pbo_GetTexSubImage where tex_image may apparently be null. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* i965: fix ignored qualifiers warningFrancesco Ansanelli2016-07-111-1/+1
| | | | | Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/blorp: fix indentation levelEric Engestrom2016-07-081-1/+1
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Fix remaining flush vs invalidate race conditions in ↵Francisco Jerez2016-07-072-0/+27
| | | | | | | | | | | | | | | | | | | | | | | brw_emit_pipe_control_flush. This hardware race condition has caused problems several times already (see "i965: Fix cache pollution race during L3 partitioning set-up.", "i965: Fix brw_render_cache_set_check_flush's PIPE_CONTROLs." and "i965: intel_texture_barrier reimplemented"). The problem is that whenever we attempt to both flush and invalidate multiple caches with a single pipe control command the flush and invalidation happen in reverse order, so the contents flushed from the R/W caches aren't guaranteed to become visible from the invalidated caches after the PIPE_CONTROL command completes execution if some concurrent rendering workload happened to pollute any of the invalidated R/O caches in the short window of time between the invalidation and flush. This makes sure that brw_emit_pipe_control_flush() has the effect expected by most callers of making the contents flushed from any R/W caches visible from the invalidated R/O caches. Cc: "12.0 11.1 11.2" <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Make room in the batch epilogue for three more pipe controls.Francisco Jerez2016-07-072-10/+10
| | | | | | | | | Review carefully, it sucks to have to keep track of the number of command packet dwords emitted in the batch epilogue manually. The MI_REPORT_PERF_COUNT_BATCH_DWORDS calculation was obviously wrong. Cc: "12.0 11.1 11.2" <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Emit SKL VF cache invalidation W/A from brw_emit_pipe_control_flush.Francisco Jerez2016-07-071-9/+10
| | | | | | | | | There were two places in the driver doing a pipe control VF cache flush, one of them was missing this workaround, move it down into brw_emit_pipe_control_flush to make sure we don't miss it again. Cc: "12.0 11.1 11.2" <[email protected]> Reviewed-by: Alejandro Piñeiro <[email protected]>
* i965: Emit SNB write cache flush W/A from brw_emit_pipe_control_flush.Francisco Jerez2016-07-074-35/+11
| | | | | | | | Shouldn't cause any functional changes at this point, but we have forgotten to apply this workaround several times in the past, make sure it doesn't happen again. Reviewed-by: Alejandro Piñeiro <[email protected]>
* osmesa: Export OSMesaCreateContextAttribs.Mathias Fröhlich2016-07-071-0/+1
| | | | | | | | | | | Since the function is exported like any other public api function and put in the header as if you could link against it, export it also from shared objects. Signed-off-by: Mathias Fröhlich <[email protected]> Reviewed-by: Brian Paul <[email protected]> Cc: "11.2 12.0" <[email protected]>
* i965: consolidate generation checkTimothy Arceri2016-07-071-6/+6
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* i965: don't copy VS attribute work arounds for HSW+Timothy Arceri2016-07-071-2/+4
| | | | | | | These workarounds are not required for HSW and above so stop copying them at VS key generation which is called at draw time. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: add double packing support to tess stagesTimothy Arceri2016-07-071-9/+18
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: add double support packing support to gs inputsTimothy Arceri2016-07-071-2/+3
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: add indirect packing support to gs load inputsTimothy Arceri2016-07-071-3/+15
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: add indirect packing support for tcs and tesTimothy Arceri2016-07-071-4/+29
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: add component packing support for tcsTimothy Arceri2016-07-071-3/+8
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: add component packing support for tesTimothy Arceri2016-07-071-5/+33
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: add component packing support for gsTimothy Arceri2016-07-072-5/+19
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* nir: use the same driver location for packed varyingsTimothy Arceri2016-07-072-5/+7
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/docs: update Intel Linux Graphics URLsEric Engestrom2016-07-062-2/+2
| | | | Signed-off-by: Eric Engestrom <[email protected]>
* i965: Remove trailing whitespaceIago Toral Quiroga2016-07-051-1/+1
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Make inline function staticIago Toral Quiroga2016-07-051-1/+1
| | | | | | Without this the i965 driver fails to load. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: make more effective use of SamplersUsedTimothy Arceri2016-07-057-19/+10
| | | | Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* i965/urb: Allow blorp to record current settingsTopi Pohjolainen2016-07-043-74/+53
| | | | | | | | | | | | | This makes it possible to skip urb re-configuration if the subsequent renders agree with the settings. Also allows blorp to allocate the maximun amount of vs entries available. Core upload logic already knows how to calculate this. Helps one synthetic benchmark. Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/blorp/gen7+: Do not trigger push constant space reconfigTopi Pohjolainen2016-07-041-2/+1
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/blorp/gen7+: Stop trashing push constant allocationTopi Pohjolainen2016-07-042-92/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Packet 3DSTATE_CONSTANT_PS is still emitted explicitly as ps stage itself is enabled and hardware may try to prefetch constants from the buffer. From the BSpec: 3D Pipeline - Windower - 3DSTATE_PUSH_CONSTANT_ALLOC_PS "Specifies the size of the PS constant buffer. This value will determine the amount of data the command stream can pre-fetch before the buffer is full." This is not possible on gen6. From the BSpec about 3DSTATE_CONSTANT_PS: "This packet must be followed by WM_STATE." Binding table emissions for stages other than PS can be now dropped, they were only needed for the 3DSTATE_CONSTANT_XS to be effective: From the BSpec: "The 3DSTATE_CONSTANT_* command is not committed to the shader unit until the corresponding (same shader) 3DSTATE_BINDING_TABLE_POINTER_* command is parsed." Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/blorp: Remove support for push constantsTopi Pohjolainen2016-07-045-145/+12
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/blorp: Use flat inputs instead of uniformsTopi Pohjolainen2016-07-042-15/+18
| | | | | | | v2 (Jason): Use LOAD_INPUT() macro Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/blorp: Fix the size requirement for vertex elementsTopi Pohjolainen2016-07-043-16/+29
| | | | | | | | v2: Rebased as this is needed before flat inputs are enabled Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/blorp: Load tranformation coordinates as vec4Topi Pohjolainen2016-07-042-16/+11
| | | | | | | | | In preparation for loading as flat vertex input. v2: Use LOAD_INPUT() macro Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/blorp: Rename LOAD_UNIFORM to LOAD_INPUTTopi Pohjolainen2016-07-041-9/+9
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/blorp: Organize pixel kill and blend/scaled inputs into vec4sTopi Pohjolainen2016-07-043-36/+65
| | | | | | | | | | | | In addition, as these are never used in parallel, add a few assertions. v2 (Jason): Skip some complexity by putting them into a union but pad rectangle grid into a vec4 instead. Also keep the LOAD_UNIFORM macro. Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/blorp: Prepare for more than two vertex attributesTopi Pohjolainen2016-07-044-3/+22
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/blorp: Tell vertex fetcher about flat inputsTopi Pohjolainen2016-07-042-8/+30
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/blorp: Add support for flat input bufferTopi Pohjolainen2016-07-041-3/+65
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/blorp: Store input read maskTopi Pohjolainen2016-07-042-0/+2
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/blorp: Rename push constants to inputsTopi Pohjolainen2016-07-045-22/+22
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/blorp: Use core vertex buffer state setupTopi Pohjolainen2016-07-041-48/+14
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/blorp: Split vertex data and element setupTopi Pohjolainen2016-07-041-21/+25
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Unify vertex buffer setupTopi Pohjolainen2016-07-042-29/+46
| | | | | | | | On gen >= 8 one doesn't provide ending address but number of bytes available. This is relative to the given offset. Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/draw: Expose vertex buffer state setupTopi Pohjolainen2016-07-042-18/+37
| | | | | | | Also change the interface to use start and end offsets. Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: don't drop const initializers in vector splittingRob Clark2016-07-021-0/+12
| | | | | Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* glsl: add driconf to zero-init unintialized varsRob Clark2016-07-024-1/+14
| | | | | | | | | | | | | Some games are sloppy.. perhaps because it is defined behavior for DX or perhaps because nv blob driver defaults things to zero. So add driconf param to force uninitialized variables to default to zero. This issue was observed with rust, from steam store. But has surfaced elsewhere in the past. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: intel_texture_barrier reimplementedAlejandro Piñeiro2016-07-011-1/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes: GL44-CTS.texture_barrier_ARB.same-texel-rw-multipass On Haswell, Broadwell and Skylake (note that in order to execute that test, it is needed to override GL and GLSL versions). On gen6 this test was already working without this change. It keeps working after it. This commit replaces the call to brw_emit_mi_flush for gen6+ with two calls to brw_emit_pipe_control_flush: * The first one with RENDER_TARGET_FLUSH and CS_STALL set to initiate a render cache flush after any concurrent rendering completes and cause the CS to stop parsing commands until the render cache becomes coherent with memory. * The second one have TEXTURE_CACHE_INVALIDATE set (and no CS stall) to clean up any stale data from the sampler caches before rendering continues. Didn't touch gen4-5, basically because I don't have a way to test them. More info on commits: 0aa4f99f562a05880a779707cbcd46be459863bf 72473658c51d5e074ce219c1e6385a4cce29f467 Thanks to Curro to help to tracking this down, as the root case was a hw race condition. v2: use two calls to pipe_control_flush instead of a combination of gen7_emit_cs_stall_flush and brw_emit_mi_flush calls (Curro) v3: no need to const cache invalidation (Curro) Reviewed-by: Francisco Jerez <[email protected]>
* i965: Simplify foreach_inst_in_block_safe() macro.Matt Turner2016-06-301-3/+2
| | | | | We know what the end looks like without examining .tail: it's NULL. It's always NULL.
* Revert "i965: get PrimitiveMode from the program rather than the shader struct"Andres Gomez2016-06-301-2/+3
| | | | | | | | | | | | | | | | | | | | | This reverts commit 644e015f0b9236e955d679cac4bcc7a1523fc475. PrimitiveMode from the program doesn't always hold a valid value that is neither of GL_TRIANGLES, GL_QUADS nor GL_ISOLINES when reaching this code. This caused regressions in the following CTS tests: GL44-CTS.stencil_texturing.functional GL44-CTS.shading_language_420pack.binding_images GL44-CTS.shading_language_420pack.binding_samplers GL44-CTS.shading_language_420pack.binding_uniform_single_block GL44-CTS.shading_language_420pack.implicit_conversions GL44-CTS.shading_language_420pack.initializer_list GL44-CTS.shading_language_420pack.length_of_vector_and_matrix GL44-CTS.shading_language_420pack.line_continuation Hence, we rather take it from the linked shader. Reviewed-by: Timothy Arceri <[email protected]> Signed-off-by: Andres Gomez <[email protected]>
* glsl/mesa: move duplicate shader fields into new struct gl_shader_infoTimothy Arceri2016-06-301-1/+1
| | | | Reviewed-by: Iago Toral Quiroga <[email protected]>
* glsl/main: remove unused params and make function staticTimothy Arceri2016-06-301-1/+1
| | | | Reviewed-by: Iago Toral Quiroga <[email protected]>
* glsl/mesa: split gl_shader in twoTimothy Arceri2016-06-3012-34/+32
| | | | | | | | | | | | | | | | | There are two distinctly different uses of this struct. The first is to store GL shader objects. The second is to store information about a shader stage thats been linked. The two uses actually share few fields and there is clearly confusion about their use. For example the linked shaders map one to one with a program so can simply be destroyed along with the program. However previously we were calling reference counting on the linked shaders. We were also creating linked shaders with a name even though it is always 0 and called the driver version of the _mesa_new_shader() function unnecessarily for GL shader objects. Acked-by: Iago Toral Quiroga <[email protected]>
* i965: Use drmIoctl for DRM_I915_GETPARAM (v2)Chad Versace2016-06-291-5/+6
| | | | | | | | Stop using drmCommandWriteRead for such a simple ioctl. v2: Handle errno correctly. [ickle] Reviewed-by: Chris Wilson <[email protected]>
* i965: Use intel_get_param() more oftenChad Versace2016-06-291-11/+5
| | | | | | | | Replace some open-coded ioctls with intel_get_param(). This is just a cleanup. No change in behavior. Reviewed-by: Ian Romanick <[email protected]>
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