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* i965: Don't bother flushing the batch if it doesn't ref our mt to map.Eric Anholt2014-04-251-1/+2
| | | | | | -1.1372% +/- 0.858033% effect on cairo runtime on glamor (n=175). Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Make Broadwell HiZ path arrange for TC flushes.Kenneth Graunke2014-04-221-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | HiZ operations make the depth/render caches out of sync with the sampler caches. We need to arrange for a TC flush to happen before the target buffer is used by the sampler. Calling brw_render_cache_set_add_bo makes that happen. On previous generations, brw_blorp_exec took care of flushing the texture cache by calling intel_batchbuffer_emit_mi_flush after doing any rendering. If we were to use the normal drawing path, then brw_postdraw_set_buffers_need_resolve would handle this. On Broadwell, we don't use BLORP, and we don't emit a rectangle primitive via the normal drawing path. The 3DSTATE_WM_HZ_OP and PIPE_CONTROL implicitly make drawing happen. So, none of our existing code makes this flush happen - we need to do it directly. Fixes 11 Piglit copyteximage subtests. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77223 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77226 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Use uint16_t for control/src index tables.Matt Turner2014-04-221-14/+14
| | | | | | No need to use 32-bits to store 15 and 12. Reviewed-by: Anuj Phogat <[email protected]>
* i965/disasm: Fix s/xoo/xor/ typo.Matt Turner2014-04-221-1/+1
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/disasm: Remove tables with obvious mappings.Matt Turner2014-04-222-13/+2
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Use ctx->Texture._MaxEnabledTexImageUnit for upper boundChris Forbes2014-04-212-2/+4
| | | | | | | | | | | Avoid looping over 32/48/96 (!!) tex image units every draw, most of which we don't care about. Improves performance on everyone's favorite not-a-benchmark by 2.9% on Haswell. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/fs: Implement fs_inst::force_sechalf support on Broadwell.Kenneth Graunke2014-04-183-4/+8
| | | | | | | | | | | | | Back when I originally wrote this code, force_sechalf was only used for Gen4 code, so I didn't bother hooking it up. However, it's used more generally these days. In particular, we use it for computing gl_SamplePosition. Fixes Piglit's spec/ARB_sample_shading/builtin-gl-sample-position tests. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77222 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965/fs: Reduce restrictions on interference in register coalescing.Matt Turner2014-04-181-13/+0
| | | | | | | | | | | | | We previously only allowed coalescing registers that interfere (i.e., whose live ranges overlap) if the destination register's live range was entirely inside the source's live range. This is unnecessary -- we only need to check for interfering writes in the intersection of their live ranges. total instructions in shared programs: 1639470 -> 1638453 (-0.06%) instructions in affected programs: 84751 -> 83734 (-1.20%) Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Give up in interference check if we see a WHILE.Matt Turner2014-04-181-1/+1
| | | | | | | | | | | Rather than any old control flow. Muchnick's algorithm just checks for interfering writes between the MOV and the end of the program. Handling this when you have backward branches is hard, so don't, but there's no reason to bail if you see forward branches. instructions in affected programs: 4270 -> 4248 (-0.52%) Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Simplify interference scan in register coalescing.Matt Turner2014-04-181-13/+9
| | | | | | | | | | | | | | | We were starting at the beginning of the instruction list, rather than with the MOV instruction itself. This allows us to coalesce after control flow. Excluding the shaders from an unreleased title, the shader-db results: total instructions in shared programs: 1603791 -> 1594215 (-0.60%) instructions in affected programs: 678772 -> 669196 (-1.41%) GAINED: 5 LOST: 0 Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Unindent can_coalesce_vars().Matt Turner2014-04-181-27/+28
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Recognize nop-MOV instructions early.Matt Turner2014-04-181-3/+17
| | | | | | | | | | And avoid rewriting other instructions unnecessarily. Removes a few self-moves we weren't able to handle because they were components of a large VGRF. instructions in affected programs: 830 -> 826 (-0.48%) Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Only sweep NOPs if register coalescing made progress.Matt Turner2014-04-181-7/+9
| | | | | | Otherwise there's nothing to do. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Retype pre-Gen6 varying pull load destination to UW.Kenneth Graunke2014-04-171-1/+1
| | | | | | | | | | | | This sets up the proper execution mask for sends in SIMD16 mode. Fixes Piglit's glsl-fs-normalmatrix, glsl-fs-uniform-array-2, glsl-fs-uniform-array-6, and glsl-fs-uniform-array-7 on Ironlake, which regressed when I enabled SIMD16 pull parameter support in commit b207e88b25e526d0f1ada7b19605b880a27866dc. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Add glBlitFramebuffer to commands affected by conditional renderingAnuj Phogat2014-04-171-0/+8
| | | | | | | | Fixes failures in Khronos OpenGL CTS test conditional_render_test9 Cc: <[email protected]> Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Fix component mask and varying_to_slot mapping for gl_ViewportIndexAnuj Phogat2014-04-171-1/+5
| | | | | | | | | | | | | | | | gl_ViewportIndex doesn't get its own varying slot. It is stored in VARYING_SLOT_PSIZ.z. This patch fixes the issue for both gen7 and gen8 because gen7_upload_3dstate_so_decl_list() is shared between them. Fixes failures in OpenGL Khronos CTS test transform_feedback_builtins. Makes new piglit test glsl-1.50-transform-feedback-builtins pass for 'gl_ViewportIndex'. Cc: <[email protected]> Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Fix component mask and varying_to_slot mapping for gl_LayerAnuj Phogat2014-04-171-4/+14
| | | | | | | | | | | | | | | | gl_Layer doesn't get its own varying slot. It is stored in VARYING_SLOT_PSIZ.y. This patch fixes the issue for both gen7 and gen8 because gen7_upload_3dstate_so_decl_list() is shared between them. Fixes failures in OpenGL Khronos CTS test transform_feedback_builtins. Makes new piglit test glsl-1.50-transform-feedback-builtins pass for 'gl_Layer'. Cc: <[email protected]> Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Put an assertion to check valid varying_to_slot[varying]Anuj Phogat2014-04-171-0/+1
| | | | | | | Cc: <[email protected]> Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* meta: Clip src/dest rects in BlitFramebuffer, using the scissorChris Forbes2014-04-172-2/+43
| | | | | | | | | | | | | | | | | Fixes piglit's fbo-blit-stretch test on drivers which use the meta path. (i965: should fix Broadwell, but also fixes Sandybridge/Ivybridge/Haswell since this test falls off the blorp path now due to format conversion) V2: Use scissor instead of just mangling the rects, to avoid texcoord rounding problems. (Thanks Marek) V3: Rebase on Eric's CTSI meta changes; re-add _mesa_update_state in the CTSI path so that _mesa_clip_blit sees the correct bounds. Signed-off-by: Chris Forbes <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77414 Reviewed-by: Anuj Phogat <[email protected]> Tested-by: Anuj Phogat <[email protected]>
* i965: Don't make instructions with a null dest a barrier to scheduling.Matt Turner2014-04-161-4/+8
| | | | | | | | | | | | | | | | Now that we properly track accumulator dependencies, the scheduler is able to schedule instructions between the mach and mov in the common the integer multiplication pattern: mul acc0, x, y mach null, x, y mov dest, acc0 Since a null destination implies no dependency on the destination, we can also safely schedule instructions (that don't write the accumulator) between the mul and mach. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Change fs_visitor::emit_lrp to use MAC for gen<6Juha-Pekka Heikkila2014-04-161-7/+4
| | | | | | | | | This allows us to emit ADD/MUL/MAC instead of MUL/ADD/MUL/ADD, saving one instruction and two temporary registers. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Juha-Pekka Heikkila <[email protected]>
* i965/fs: Add support for the MAC instruction.Juha-Pekka Heikkila2014-04-162-0/+4
| | | | | | | | | | This allows us to generate the MAC (multiply-accumulate) instruction, which can be used to implement some expressions in fewer instructions than doing a series of MUL and ADDs. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Juha-Pekka Heikkila <[email protected]>
* i965/vec4: Change vec4_visitor::emit_lrp to use MAC for gen<6Juha-Pekka Heikkila2014-04-161-16/+6
| | | | | | | | | This allows us to emit ADD/MUL/MAC instead of MUL/ADD/MUL/ADD, saving one instruction and two temporary registers. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Juha-Pekka Heikkila <[email protected]>
* i965/vec4: Add support for the MAC instruction.Juha-Pekka Heikkila2014-04-163-0/+5
| | | | | | | | | | This allows us to generate the MAC (multiply-accumulate) instruction, which can be used to implement some expressions in fewer instructions than doing a series of MUL and ADDs. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Juha-Pekka Heikkila <[email protected]>
* i965: Add writes_accumulator flagJuha-Pekka Heikkila2014-04-168-35/+131
| | | | | | | | | | | | | | | | | | | | | | | Our hardware has an "accumulator" register, which can be used to store intermediate results across multiple instructions. Many instructions can implicitly write a value to the accumulator in addition to their normal destination register. This is enabled by the "AccWrEn" flag. This patch introduces a new flag, inst->writes_accumulator, which allows us to express the AccWrEn notion in the IR. It also creates a n ALU2_ACC macro to easily define emitters for instructions that implicitly write the accumulator. Previously, we only supported implicit accumulator writes from the ADDC, SUBB, and MACH instructions. We always enabled them on those instructions, and left them disabled for other instructions. To take advantage of the MAC (multiply-accumulate) instruction, we need to be able to set AccWrEn on other types of instructions. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Juha-Pekka Heikkila <[email protected]>
* i965: Add is_accumulator() function.Juha-Pekka Heikkila2014-04-164-0/+28
| | | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Juha-Pekka Heikkila <[email protected]>
* i965: Add reads_accumulator_implicitly() function.Matt Turner2014-04-162-0/+14
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* Revert "i965/fs: Only sweep NOPs if register coalescing made progress."Matt Turner2014-04-151-8/+7
| | | | | | This reverts commit f092e8951ce5212ba3cbb382ce3a6666eb6c9bed. Didn't mean to push this...
* i965/fs: Only sweep NOPs if register coalescing made progress.Matt Turner2014-04-151-7/+8
| | | | Otherwise there's nothing to do.
* i965: Fix buffer overruns in MSAA MCS buffer clearing.Eric Anholt2014-04-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This manifested as rendering failures or sometimes GPU hangs in compositors when they accidentally got MSAA visuals due to a bug in the X Server. Today we decided that the problem in compositors was equivalent to a corruption bug we'd noticed recently in resizing MSAA-visual glxgears, and debugging got a lot easier. When we allocate our MCS MT, libdrm takes the size we request, aligns it to Y tile size (blowing it up from 300x300=900000 bytes to 384*320=122880 bytes, 30 pages), then puts it into a power-of-two-sized BO (131072 bytes, 32 pages). Because it's Y tiled, we attach a 384-byte-stride fence to it. When we memset by the BO size in Mesa, between bytes 122880 and 131072 the data gets stored to the first 20 or so scanlines of each of the 3 tiled pages in that row, even though only 2 of those pages were allocated by libdrm. In the glxgears case, the missing 3rd page happened to consistently be the static VBO that got mapped right after the first MCS allocation, so corruption only appeared once window resize made us throw out the old MCS and then allocate the same BO to back the new MCS. Instead, just memset the amount of data we actually asked libdrm to allocate for, which will be smaller (more efficient) and not overrun. Thanks go to Kenneth for doing most of the hard debugging to eliminate a lot of the search space for the bug. Cc: "10.0 10.1" <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77207 Reviewed-by: Kenneth Graunke <[email protected]>
* meta: Add support for MSAA resolves from 2D_MS_ARRAY textures.Eric Anholt2014-04-152-17/+49
| | | | | | | | | We don't have any piglit tests for this currently. v2: Use vec3s for the texcoords so it has some hope of working. Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* meta: Add an accelerated glCopyTexSubImage using glBlitFramebuffer.Eric Anholt2014-04-154-12/+94
| | | | | | | | | | | | | | | You'll note from the previous commits that there's something of a loop here: You call CTSI, which calls BlitFB, then if things go wrong that falls back to CTSI. As a result, meta CTSI reaches over into blitfb to tell it "no, don't try that fallback". v2: Drop the _mesa_update_state(), which was only necessary due to use of _mesa_clip_blit() in _mesa_meta_BlitFramebuffer() in another patch series. v3: Drop an _EXT suffix I copy-and-pasted. Reviewed-by: Ian Romanick <[email protected]> (v2) Reviewed-by: Kenneth Graunke <[email protected]>
* meta: Add support for CUBE_MAP_ARRAY to generatemipmap.Eric Anholt2014-04-152-1/+5
| | | | | | | | | | I added support to bind_fbo_image in the process of building meta CopyTexSubImage, and found that it broke generatemipmap because previously we would just throw a GL error there and then end up with an incomplete FBO and fallback. Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* meta: Infer bind_fbo_image parameters from an incoming image.Eric Anholt2014-04-153-6/+13
| | | | | Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* meta: Move bind_fbo_image() code back to meta.c, to reuse it elsewhere.Eric Anholt2014-04-153-34/+36
| | | | | | | | | I need to do the same code again for CopyTexSubImage(). v2: Drop incorrect, not-terribly-useful comment (review by Ken) Reviewed-by: Ian Romanick <[email protected]> (v1) Reviewed-by: Kenneth Graunke <[email protected]>
* meta: Refactor the BlitFramebuffer depth CopyTexImage fallback.Eric Anholt2014-04-152-138/+2
| | | | | | | | | This avoids a ReadPixels() if there's accelerated CopyTexImage present. It now requires GLSL as opposed to just fragment programs, but we don't have any drivers that do ARB_fp but not GLSL. Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* meta: Refactor the BlitFramebuffer color CopyTexImage fallback.Eric Anholt2014-04-151-52/+41
| | | | | | | | | | | | | | | | | | | There shouldn't be anything special about copying out a subset of the src rb to a temp before texturing from it, so just do it when we're figuring out our src texture binding. This drops Anuj's change to copy an extra border of 1 pixel around the src area. I can't see how that change could be valid, and presumably if there's some filtering problem at edges we just need to set the right wrap mode. v2: Don't fall back to swrast on non-2D/RECT/2D_MS textures when we can still CopyTexSubImage. Fixes a segfault regression on i965 with gl-3.2-layered-rendering-blit. Reviewed-by: Ian Romanick <[email protected]> (v1) Reviewed-by: Kenneth Graunke <[email protected]> (v1) Tested-by: Anuj Phogat <[email protected]>
* meta: Drop blit src size fallback.Eric Anholt2014-04-151-10/+0
| | | | | | | | | | | | | I think we can assert that renderbuffer size is <= maximum 2D texture size. Our source coordinates should have already been clipped to the src renderbuffer size, but haven't actually (so we could potentially have trouble if there's scaling, and we're in the CopyTexImage path that tries to use src size). However, this texture size dependency was blocking the next refactors, so I'm not sure if we want to go ahead with this series before we get the clipping sorted out or not. Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Avoid dependency hints on math opcodesMike Stroyan2014-04-151-0/+8
| | | | | | | | | | | Putting NoDDClr and NoDDChk dependency control on instruction sequences that include math opcodes can cause corruption of channels. Treat math opcodes like send opcodes and suppress dependency hinting. Signed-off-by: Mike Stroyan <[email protected]> Tested-by: Tony Bertapelli <[email protected]> Cc: [email protected] Reviewed-by: Matt Turner <[email protected]>
* i965: Expand INTEL_DEBUG to uint64_t.Matt Turner2014-04-152-2/+2
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* dri: Expand driParseDebugString return value to uint64_t.Matt Turner2014-04-152-6/+5
| | | | | | Users will downcast if they don't have >32 debug flags. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Remove dead_code_eliminate_local().Matt Turner2014-04-152-159/+0
| | | | | | | Subsumed by the new dead_code_eliminate() function. No shader-db changes. Reviewed-by: Eric Anholt <[email protected]>
* i965/fs: Clear variable from live-set if it's completely overwritten.Matt Turner2014-04-151-0/+9
| | | | | | | | One program affected: instructions in affected programs: 246 -> 244 (-0.81%) Reviewed-by: Eric Anholt <[email protected]>
* i965/fs: Reimplement dead_code_elimination().Matt Turner2014-04-153-56/+117
| | | | | | | | | | | | | | | | | total instructions in shared programs: 1653399 -> 1651790 (-0.10%) instructions in affected programs: 92157 -> 90548 (-1.75%) GAINED: 2 LOST: 2 Also significantly reduces the number of optimization loop iterations: total loop iterations in shared programs: 39724 -> 31651 (-20.32%) loop iterations in affected programs: 21617 -> 13544 (-37.35%) Including some great pathological cases, like 29 -> 3 in Strike Suit Zero and 24 -> 3 in Dota2. Reviewed-by: Eric Anholt <[email protected]>
* i965/vec4: Let DCE eliminate dead writes in other basic blocks.Matt Turner2014-04-151-4/+4
| | | | | | | | We previously stopped searching for unread writes after encountering control flow, but we can instead just search backwards until we hit control flow. instructions in affected programs: 22854 -> 22194 (-2.89%)
* i965/gs: Add dummy source to prepare_channel_masks instruction.Matt Turner2014-04-151-1/+2
| | | | | | The generator uses its destination as a source implicitly, which breaks some assumptions in dead code elimination. Giving the instruction a source allows us to reason about it better.
* i965: Disable Z16 in all APIs.Kenneth Graunke2014-04-151-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We originally thought that GL 3.0 required GL_DEPTH_COMPONENT16 to map exactly to Z16. However, we misread the specification, thanks in part to LaTeX reordering the tables in the PDF. Page 180 of the GL 3.0 specification (glspec30.20080923.pdf) says: "[...] memory allocation per texture component is assigned by the GL to match the allocations listed in tables 3.16-3.18 as closely as possible. [...] Required Texture Formats [...] In addition, implementations are required to support the following sized internal formats. Requesting one of these internal formats for any texture type will allocate exactly the internal component sizes and types shown for that format in tables 3.16-3.17:" Notably, however, GL_DEPTH_COMPONENT16 does /not/ appear in table 3.16 or table 3.17. It appears in table 3.18, where the "exact" rule doesn't apply, and it falls back to the "closely as possible" rule. The confusing part is that the ordering of the tables in the PDF is: Table 3.16 (pages 182-184) Table 3.18 (bottom of page 184 to top of 185) Table 3.17 (page 185) Presumably, people saw table 3.16, then saw the table immediately following with DEPTH_COMPONENT* formats, and assumed it was 3.17. Based on a patch by Chia-I Wu, but without the driconf option to force Z16 to be used. It's not required, and there's apparently no benefit to actually using it. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Chia-I Wu <[email protected]>
* i965: Update comments about Z16 being slow.Kenneth Graunke2014-04-151-7/+10
| | | | | | | | | | | | | | | We've learned a few things since we originally disabled Z16; this attempts to summarize the issue. I am no expert on this subject, though, so the comment may not be totally accurate. I did some benchmarking on GM45 and Ironlake, and discovered that for GLBenchmark 2.7 EgyptHD, using Z16 was 3% slower on GM45 (n=15), and 4.5% slower on Ironlake (n=95). So, we can drop the "on Ivybridge" aspect of the comment - it's always slower. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Chia-I Wu <[email protected]>
* i965/gen8: add debug code to show FS disasm with jump locationsJordan Justen2014-04-141-0/+9
| | | | | | | Copied from similar code in gen8_vec4_generator.cpp. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: glClearBuffer() should only clear a single buffer.Iago Toral Quiroga2014-04-133-3/+7
| | | | | | | | | | | | | | | | glClearBuffer() is currently clearing all active draw color buffers (all buffers that have not been set to GL_NONE when calling glDrawBuffers) instead of only clearing the one it receives as parameter. Altough brw_clear() receives a bit mask indicating the color buffers that should be cleared, this mask is ignored when calling brw_blorp_clear_color(). This was breaking the 'fbo-drawbuffers-none glClearBuffer' piglit test. The patch provides the bit mask to brw_blorp_clear_color() so it can limit clearing to the color buffers present in the mask. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76832 Reviewed-by: Eric Anholt <[email protected]>
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