summaryrefslogtreecommitdiffstats
path: root/src/mesa/drivers
Commit message (Expand)AuthorAgeFilesLines
* t_dd_dmatmp: Remove HAVE_QUADS supportIan Romanick2015-09-232-2/+0
* t_dd_dmatmp: Remove HAVE_QUAD_STRIPS supportIan Romanick2015-09-232-2/+0
* t_dd_dmatmp: Make "count" actually be the countIan Romanick2015-09-232-2/+2
* i965/vec4: Don't coalesce regs in Gen6 MATH ops if reswizzle/writemask neededAntia Puentes2015-09-232-3/+12
* i965/vec4: Detect and delete useless MOVs.Matt Turner2015-09-221-0/+22
* i965/vec4: Add support for fdph_replicatedJason Ekstrand2015-09-221-0/+5
* i965: Add defines for tessellation stagesChris Forbes2015-09-221-0/+72
* i965/vec4: refactor brw_vec4_copy_propagation.Alejandro Piñeiro2015-09-221-14/+18
* i965: fix textureGrad for cubemapsTapani Pälli2015-09-221-19/+182
* i965: Clean up GLSL compiler option setupJason Ekstrand2015-09-211-26/+20
* i965/skl: Use larger URB size where available.Ben Widawsky2015-09-211-1/+2
* i965: Fix MRF register number assertions for compr4.Kenneth Graunke2015-09-211-2/+2
* i965/vec4: Use MRF registers 21-23 for spilling in gen6Iago Toral Quiroga2015-09-211-4/+6
* i965/fs: Use MRF registers 21-23 for spilling in gen6Iago Toral Quiroga2015-09-211-4/+7
* i965: Turn BRW_MAX_MRF into a macro that accepts a hardware generationIago Toral Quiroga2015-09-218-28/+28
* i965: Move MRF register asserts out of brw_reg.hIago Toral Quiroga2015-09-214-7/+16
* i965: Maximum allowed size of SEND messages is 15 (4 bits)Iago Toral Quiroga2015-09-214-2/+10
* i965/vec4/nir: Remove all "this->" snippetsEduardo Lima Mitev2015-09-201-16/+15
* dri/common: fix gbm-symbols-check regressionMarcin Ślusarz2015-09-201-1/+1
* dri/common: use sysconfdir when looking for drircMarcin Ślusarz2015-09-192-1/+6
* nir/lower_tex: support projector lowering per sampler typeRob Clark2015-09-181-1/+4
* nir: rename nir_lower_tex_projectorRob Clark2015-09-181-1/+1
* i965/vec4: Change types as needed to propagate source modifiers using current...Alejandro Piñeiro2015-09-191-2/+28
* i965/fs: Fix comparison between signed and unsigned integer expressionsIago Toral Quiroga2015-09-181-2/+2
* i965/vec4: Use nir_move_vec_src_uses_to_destJason Ekstrand2015-09-171-0/+3
* i965/fs: The barrier send uses only 1 payload registerJordan Justen2015-09-152-2/+5
* i965/vec4: Use the replicated fdot instruction in NIRJason Ekstrand2015-09-152-3/+11
* i965/vec4_nir: Use partial SSA form rather than full non-SSAJason Ekstrand2015-09-153-4/+20
* i965/fs: Add a very basic validation passJason Ekstrand2015-09-154-0/+69
* i965/fs_surface_builder: Only apply predicate to components that existJason Ekstrand2015-09-151-1/+1
* i965/fs: Only read output_components many components when writing an outputJason Ekstrand2015-09-151-1/+3
* i965/fs: Set output_components for lowered clip distance outputsJason Ekstrand2015-09-151-0/+2
* i965: Move perf_debug code to brw_codegen_*_prog()Kristian Høgsberg Kristensen2015-09-145-76/+75
* i965: Move brw_fs_precompile() to brw_wm.cKristian Høgsberg Kristensen2015-09-142-58/+59
* i965: Move compute shader code aroundKristian Høgsberg Kristensen2015-09-145-333/+362
* meta: Abort meta pbo path if TexSubImage need signed unsigned conversionAnuj Phogat2015-09-141-18/+25
* i965/vec4_nir: Load constants as integersAntia Puentes2015-09-141-2/+2
* i965/vec4: Fix saturation errors when coalescing registersAntia Puentes2015-09-141-0/+21
* i965/nir: Support gl_WorkGroupID variableJordan Justen2015-09-131-1/+9
* i965/cs: Initialize gl_WorkGroupID variable from payloadJordan Justen2015-09-132-0/+20
* i965/nir: Support gl_LocalInvocationID variableJordan Justen2015-09-131-0/+17
* i965/cs: Initialize gl_LocalInvocationID from payloadJordan Justen2015-09-132-2/+24
* i965/cs: Initialize gl_LocalInvocationID in push constant dataJordan Justen2015-09-131-4/+52
* i965/cs: Reserve local invocation id in payload regsJordan Justen2015-09-134-0/+45
* i965/vec4: Don't reswizzle hardware registersJason Ekstrand2015-09-121-0/+8
* i965/emit: Add assertions for accumulator restrictionsJason Ekstrand2015-09-121-0/+17
* i965/vec4: check writemask when bailing out at register coalesceAlejandro Piñeiro2015-09-111-4/+6
* i965: Use hash tables for brw_fs_vector_splitting().Kenneth Graunke2015-09-111-22/+22
* meta: Use result of texture coordinate clamping operationIan Romanick2015-09-101-2/+2
* meta: Always bind the textureIan Romanick2015-09-101-3/+6
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-04 22:28:56 +0000