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* i965: get outputs_written from gl_programTimothy Arceri2017-01-191-2/+2
* i965/blorp: Make post draw flush more explicitTopi Pohjolainen2017-01-182-5/+22
* i965/gen6: Issue direct depth stall and flush after depth clearTopi Pohjolainen2017-01-181-1/+6
* i965: Make depth clear flushing more explicitTopi Pohjolainen2017-01-182-8/+57
* i965/blorp: Use the render cache mechanism instead of explicit flushingTopi Pohjolainen2017-01-181-1/+7
* i965: Make brw_cache_item structure private to brw_program_cache.c.Kenneth Graunke2017-01-182-19/+21
* i965: Fix SURFACE_STATE to handle non-zero aux offsetsBen Widawsky2017-01-181-2/+1
* i965: Don't map/unmap in brw_print_program_cache on LLC platforms.Kenneth Graunke2017-01-171-2/+4
* i965: Move program cache printing to brw_program_cache.c.Kenneth Graunke2017-01-173-57/+49
* i965: Make a helper for finding an existing shader variant.Kenneth Graunke2017-01-177-85/+68
* i965: Make DCE set null destinations on messages with side effects.Kenneth Graunke2017-01-171-13/+41
* i965: Combine some dead code elimination NOP'ing code.Kenneth Graunke2017-01-171-8/+1
* i965: Make DCE explicitly not eliminate any control flow instructions.Kenneth Graunke2017-01-171-3/+2
* i965: Make BLORP disable the NP Z PMA stall fix.Kenneth Graunke2017-01-161-0/+4
* i965: Enable OpenGL 4.5 on Haswell.Kenneth Graunke2017-01-162-2/+2
* i965: Use align1 mode for barrier messages.Kenneth Graunke2017-01-151-0/+3
* i965: Move Gen4-5 interpolation stuff to brw_wm_prog_data.Kenneth Graunke2017-01-1311-70/+52
* i965/vec4: Fix mapping attributesJuan A. Suarez Romero2017-01-132-23/+11
* i965: Fix textureGather with RG32I/UI on Gen7.Kenneth Graunke2017-01-132-8/+37
* xlib: Unify the style of function pointer calls in structsBoyan Ding2017-01-131-74/+74
* radeon: Unify the style of function pointer calls in structsBoyan Ding2017-01-133-17/+17
* nouveau: Unify the style of function pointer calls in structsBoyan Ding2017-01-131-3/+3
* i915: Add XRGB8888 format to intel_screen_make_configsDerek Foreman2017-01-131-1/+2
* nir/i965: assert first is always less than 64Juan A. Suarez Romero2017-01-121-0/+1
* i965/gen7: expose OpenGL 4.2 on Haswell when supportedJuan A. Suarez Romero2017-01-122-2/+2
* i965: enable ARB_shader_precision to HSW+Samuel Iglesias Gonsálvez2017-01-121-1/+1
* i965: unify the code to enable of ARB_gpu_shader_fp64 and ARB_vertex_attrib_6...Samuel Iglesias Gonsálvez2017-01-121-7/+2
* i965: Enable ARB_vertex_attrib_64bit for HaswellAlejandro Piñeiro2017-01-121-1/+3
* i965: check for dual slot attributes on any genJuan A. Suarez Romero2017-01-121-2/+1
* i965/vec4: emit correctly load_inputs for 64bit dataJuan A. Suarez Romero2017-01-121-6/+15
* i965/vec4: take into account doubles when creating attribute mappingAlejandro Piñeiro2017-01-121-4/+9
* i965/vec4/nir: vec4 also needs to remap vs attributesAlejandro Piñeiro2017-01-121-10/+22
* i965/vec4: use attribute slots for first non payload GRFAlejandro Piñeiro2017-01-121-1/+1
* i965: downsize *64*PASSTHRU formats to equivalent *32*FLOAT formats on gen < 8Alejandro Piñeiro2017-01-121-30/+139
* i965: return PASSTHRU surface types also on gen7Alejandro Piñeiro2017-01-121-2/+6
* i965: Enable predicate support on gen >= 8.Rafael Antognolli2017-01-111-1/+1
* i965: Use the nir_move_comparisons pass.Kenneth Graunke2017-01-121-0/+1
* i965: Move nir_lower_locals_to_regs a bit later.Kenneth Graunke2017-01-121-2/+2
* compiler: Merge shader_info's tcs and tes structs.Kenneth Graunke2017-01-105-20/+22
* i965: Fix number of slots in SSO mode when there are no user varyings.Kenneth Graunke2017-01-091-4/+2
* nir/i965: use two slots from inputs_read for dvec3/dvec4 vertex input attributesJuan A. Suarez Romero2017-01-096-29/+16
* i965: call intel_prepare_render always when reading pixelsTapani Pälli2017-01-091-6/+6
* i965: Move TES input VUE map calculation out a layer.Kenneth Graunke2017-01-073-9/+11
* i965: Pass NULL for gl_program when compiling TES.Kenneth Graunke2017-01-071-1/+1
* i965: Move TES spacing/domain/topology setup to brw_compile_tes().Kenneth Graunke2017-01-072-33/+34
* i965: Access TES shader info via NIR.Kenneth Graunke2017-01-071-6/+6
* mesa: Introduce a compiler enum for tessellation spacing.Kenneth Graunke2017-01-072-15/+9
* compiler: Change shader_info->tes.vertex_order into a ccw boolean.Kenneth Graunke2017-01-071-10/+3
* drirc: Allow extension midshader for Divinity: Original Sin (EE)Kai Wasserbäch2017-01-071-0/+4
* i965/compiler: Use the new nir_opt_copy_prop_vars passJason Ekstrand2017-01-061-0/+1
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