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* i965: Set maximum number of threads for Ivybridge.Kenneth Graunke2011-05-171-1/+11
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Split out tracked state atoms for Ivybridge.Kenneth Graunke2011-05-171-1/+70
| | | | | | | | Currently, gen7_atoms is a verbatim copy of gen6_atoms; future commits will update it to contain gen7-specific state. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* intel: Initial IS_GEN7 plumbing.Kenneth Graunke2011-05-173-3/+17
| | | | | | | | | Currently, IS_GEN7, IS_IVYBRIDGE, IS_IVB_GT1, and IS_IVB_GT2 all return false. This allows me to write the code for them before actually adding the PCI IDs and thus enabling the hardware. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Rename max_vs_handles to max_vs_entries for consistency.Kenneth Graunke2011-05-173-6/+6
| | | | | | | | | | | The documentation uses the term "vertex URB entries", the code talks about "entry size", and so on. Also, handles are just "pointers" to entries (actually small integers). Also rename max_gs_handles to max_gs_entries. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Convert BRW_NEW_* dirty bits to use an enum.Kenneth Graunke2011-05-171-21/+45
| | | | | | | | This will make it much easier to add new dirty bits. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Rework IF/ELSE jump target back-patching.Kenneth Graunke2011-05-171-114/+144
| | | | | | | | | | | | | | | | | | | | | | | | | The primary motivation for this is to better support Ivybridge control flow. Ivybridge IF instructions need to point to the first instruction of the ELSE block -and- the ENDIF instruction; the existing code only supported back-patching one instruction ago. A second goal is to simplify and centralize the back-patching, hopefully clarifying the code somewhat. Previously, brw_ELSE back-patched the IF instruction, and brw_ENDIF back-patched the previous instruction (IF or ELSE). With this patch, brw_ENDIF is responsible for patching both the IF and (optional) ELSE. To support this, the control flow stack (if_stack) maintains pointers to both the IF and ELSE instructions. Unfortunately, in single program flow (SPF) mode, both were emitted as ADD instructions, and thus indistinguishable. To remedy this, this patch simply emits IF and ELSE, rather than ADDs; brw_ENDIF will convert them to ADDs (the SPF version of back-patching). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Move IF stack handling into the EU abstraction layer/brw_compile.Kenneth Graunke2011-05-1710-132/+122
| | | | | | | | This hides the IF stack and back-patching of IF/ELSE instructions from each of the code generators, greatly simplifying the interface. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Get a ralloc context into brw_compile.Kenneth Graunke2011-05-178-22/+44
| | | | | | | | | | | | This would be so much easier if we were using C++; we could simply use constructors and destructors. Instead, we have to update all the callers. While we're at it, ralloc various brw_wm_compile fields rather than explicitly calloc/free'ing them. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965/gs: Move generation check for bailing earlier.Kenneth Graunke2011-05-171-6/+6
| | | | | | | | | On Sandybridge, we don't need to break down primitives. There's no need to bother setting up brw_compile and such if it's not going to be used; bail as early as possible. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Add _NEW_LIGHT to Gen6 clip state dirty bits.Kenneth Graunke2011-05-171-1/+2
| | | | | | | | | ctx->Light.ProvokingVertex depends on _NEW_LIGHT. Found by inspection. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* r300/compiler: Fix bug in rc_get_variables()Tom Stellard2011-05-171-45/+13
| | | | | | | Variables that write to the same source select need to pe paired together otherwise the register allocator might fail. https://bugs.freedesktop.org/show_bug.cgi?id=36753
* i965: Pass brw_compile pointer to brw_set_src[01].Kenneth Graunke2011-05-163-98/+107
| | | | | | | | This makes it symmetric with brw_set_dest, which is convenient, and will also allow for assertions to be made based off of intel->gen. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Fix "Paramater" typo in gen6_wm_state.c.Kenneth Graunke2011-05-161-1/+1
| | | | Signed-off-by: Kenneth Graunke <[email protected]>
* r300/compiler: Use ALU Result for IF conditionalsTom Stellard2011-05-146-20/+212
| | | | This saves one instruction per IF.
* i965: Use BRW_DATAPORT_READ_TARGET_DATA_CACHE instead of 0.Kenneth Graunke2011-05-131-3/+3
| | | | | | | | Using the #define'd constant is better than 0 with a comment. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Rename dp_render_target struct to gen6_dp.Kenneth Graunke2011-05-133-31/+31
| | | | | | | | | This is actually just the message descriptor for Gen6+ dataport access; it has nothing to do with the render cache. Access to the sampler cache and constant cache also would use this struct; rename for clarity. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Attempt to un-muddle Gen6 data port message target defines.Kenneth Graunke2011-05-132-6/+9
| | | | | | | | | | | | | | | | These are documented on page 245 of IHD_OS_Vol4_Part2.pdf (the public Sandybridge documentation/SEND instruction description). Somebody had the bright idea to reuse gen4/5 defines labelled READ/WRITE which just happened to be the same values as Render Cache/Sampler Cache. It turns out that this field has nothing to do with READ/WRITE on Sandybridge, but rather represents which data port to direct it to. This was especially confusing in brw_set_dp_read_message, which used "BRW_MESSAGE_TARGET_DATAPORT_WRITE." In a read function. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Fix incorrectly named data port define.Kenneth Graunke2011-05-131-1/+1
| | | | | | | According to my documentation this is actually "Media Block Write" on Gen4-5; there has never been a "DWord Block Write." Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Fix typo in Gen6 "DWord Scattered Write" message define.Kenneth Graunke2011-05-131-1/+1
| | | | | | It's DWORD, not DWORLD. Signed-off-by: Kenneth Graunke <[email protected]>
* r300/compiler: Fix bug in rc_get_variables()Tom Stellard2011-05-111-7/+11
| | | | | | Variables that share readers were not always being linked together. https://bugs.freedesktop.org/show_bug.cgi?id=36939
* r300/compiler: Limit instructions to 3 source selectsTom Stellard2011-05-114-39/+104
| | | | | | | | | Some presubtract conversions were generating more than 3 source selects. https://bugs.freedesktop.org/show_bug.cgi?id=36527 Note: This is a candidate for the 7.10 branch.
* r300/compiler: Add simple unit test frameworkTom Stellard2011-05-117-0/+579
| | | | Plus three tests for rc_inst_can_use_presub()
* r300/compiler: align memory allocations to 8-bytesMatt Turner2011-05-091-1/+1
| | | | | | | | | Eliminates unaligned accesses on strict architectures. Spotted by Jay Estabrook. Signed-off-by: Matt Turner <[email protected]> NOTE: This is a candidate for the 7.10 branch.
* r300c: Fix up for register allocator rewrite.Michel Dänzer2011-05-092-0/+2
| | | | | Was broken by commit fe622bac0c1b5b9f2a9fcf9f35b51232a06bea42 ('r300/compiler: Rewrite register allocator').
* r300/compiler: implement TXD and TXL opcodesMarek Olšák2011-05-075-0/+52
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* Add pci id for FirePro 2270Kostas Georgiou2011-05-062-0/+2
| | | | Signed-off-by: Kostas Georgiou <[email protected]>
* egl: Add a cursor use bit to MESA_drm_imageKristian Høgsberg2011-05-061-1/+9
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* mesa/gdi: Silence gcc warning about unused result.José Fonseca2011-05-041-1/+1
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* r600c: add some new pci idsAlex Deucher2011-05-032-0/+8
| | | | Signed-off-by: Alex Deucher <[email protected]>
* i965/gen6: Align interleaved URB writes for overflow outputs as well.Eric Anholt2011-05-011-8/+27
| | | | | | | Fixes glsl-max-varyings. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=35614 Reviewed-by: Kenneth Graunke <[email protected]>
* r300/compiler: remove set-but-unused variablesMarek Olšák2011-05-012-5/+1
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* r300/compiler: Cleanups from the regalloc mergeTom Stellard2011-04-303-8/+4
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* r300/compiler: Add return statement to rc_list()Tom Stellard2011-04-301-0/+2
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* r300g: Fix scons buildTom Stellard2011-04-301-0/+1
| | | | | Broken by the dependency on ralloc introduced by fe622bac0c1b5b9f2a9fcf9f35b51232a06bea42
* r300/compiler: Enable swizzle packing in the allocator for r300 and r400Tom Stellard2011-04-306-41/+120
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* r300/compiler: Handle loops in the register allocatorTom Stellard2011-04-304-19/+103
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* r300/compiler: Handle loops in rc_get_readers()Tom Stellard2011-04-304-75/+150
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* r300/compiler: Rewrite register allocatorTom Stellard2011-04-3018-236/+1547
| | | | | | | The new allocator uses ra and does swizzle packing. Also, a data structure (struct rc_variable) and associated functions have been added for generating UD and DU chains.
* r300/compiler: Use RC_MASK_W when converting RGB to Alpha instructionsTom Stellard2011-04-301-1/+1
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* r300/compiler: rc_reader_data: Add ExitOnAbort flagTom Stellard2011-04-305-3/+10
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* r300/compiler: Add more info to struct rc_readerTom Stellard2011-04-305-16/+41
| | | | | For pair instructions we need a reference to both the arg and source.
* r300/compiler: Add remove dead sources passTom Stellard2011-04-305-0/+66
| | | | | | | | The instruction scheduler will sometimes leave orphaned sources when converting instructions from RGB to Alpha. If one of these orphaned sources has an index greater than the maximum temporary register index, then the compiler will incorrectly report "Too many hardware temporaries used". The dead sources pass cleans up these orphaned sources.
* i965/gen6: Fix LogicOp handling for GL_COPY and/or floating-point RTs.Eric Anholt2011-04-291-5/+13
| | | | | | | | We were accidentally leaving blending enabled for LogicOp GL_COPY, which ARB_color_buffer_float/GL_RGBA32F-render (and friends) caught. Additionally, the GL spec says that no LogicOp should be done to floating-point targets, and the GPU gets really angry even if you say to LogicOp GL_COPY to float.
* i965: Remove dead entrypoints to state cache, rename the one that's left.Eric Anholt2011-04-298-157/+54
| | | | | | | | | | As we expanded the usage of the state cache, it grew extra functionality. However, with the recent state streaming rework, we're back to the state cache being used only for shader kernels, which is the piece of GPU state that's actually expensive to compute again from scratch, since it involves compiling. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen4: Move the GS state to state streaming.Eric Anholt2011-04-295-98/+45
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen4: Move clip state to state streamingEric Anholt2011-04-294-106/+60
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Drop the now unused brw_cache_data() function.Eric Anholt2011-04-292-47/+0
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Fix up state dumping for SF state.Eric Anholt2011-04-291-2/+3
| | | | | | It was moved to state streaming a while back and this was left over. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen4: Move VS state to state streaming.Eric Anholt2011-04-295-88/+53
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen6: Use the dynamic state base address to reduce relocations.Eric Anholt2011-04-299-46/+55
| | | | | | | | | | Now that all the dynamic state is streamed through the top of the batchbuffer, we can cut out many of our relocations to that state by using the base address. Improves 3DMMES taiji performance 3.3% +/- 0.4% (n=15). Reviewed-by: Kenneth Graunke <[email protected]>
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