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* i965: Trim the interleaved upload to the minimum number of verticesChris Wilson2011-02-221-1/+5
* i965: Reinstate max-index paranoiaChris Wilson2011-02-221-1/+1
* i965: Zero the offset into the vbo when uploading non-interleavedChris Wilson2011-02-221-0/+1
* i965: Fix VB packet reuse when offset for the new buffer isn't stride aligned.Eric Anholt2011-02-211-1/+1
* radeon: add default switch case to silence unhandled enum warningBrian Paul2011-02-211-0/+2
* intel: Fix insufficient integer width for upload buffer offsetChris Wilson2011-02-211-2/+2
* i965: Remove spurious duplicate ADVANCE_BATCHChris Wilson2011-02-211-1/+0
* i915: Emit a single relocation per vboChris Wilson2011-02-215-17/+45
* i915: Suppress emission of redundant stencil updatesChris Wilson2011-02-211-45/+55
* i915: Separate BLEND from general context state.Chris Wilson2011-02-213-22/+40
* i915: Only flag context changes if the actual state is changedChris Wilson2011-02-211-49/+105
* i915: suppress repeated sampler state emissionChris Wilson2011-02-212-0/+11
* i915: Eliminate redundant CONSTANTS updatesChris Wilson2011-02-211-25/+26
* i965: Use compiler builtins when availableChris Wilson2011-02-212-11/+8
* i965: Micro-optimise check_stateChris Wilson2011-02-211-7/+5
* intel: use throttle ioctl for throttlingChris Wilson2011-02-213-13/+3
* i965: Remove unused 'next_free_page' memberChris Wilson2011-02-211-5/+0
* intel: Skip the flush before read-pixels via blitChris Wilson2011-02-211-4/+7
* intel: extend current vertex buffersChris Wilson2011-02-215-23/+73
* intel: Use specified alignment for writes into the upload bufferChris Wilson2011-02-213-30/+57
* i965: Clean up brw_prepare_vertices()Chris Wilson2011-02-211-21/+20
* intel: combine short memcpy using a temporary allocated bufferChris Wilson2011-02-213-38/+27
* i965: upload normal arrays as interleavedChris Wilson2011-02-211-30/+72
* i965: interleaved vboChris Wilson2011-02-211-12/+27
* i965: emit one vb packet per vboChris Wilson2011-02-213-77/+83
* i965: upload transient indices into the same discontiguous bufferChris Wilson2011-02-212-13/+8
* i965: suppress repeat-emission of identical vertex elementsChris Wilson2011-02-211-3/+2
* i965: Move repeat-instruction-suppression to batchbuffer coreChris Wilson2011-02-219-152/+120
* intel: use pwrite for batchChris Wilson2011-02-2127-302/+219
* i965: drop state_bo references to batch_boChris Wilson2011-02-219-105/+74
* i965: directly write wm state to batchChris Wilson2011-02-211-63/+48
* i965: write cc straight to batchChris Wilson2011-02-211-48/+46
* i965: switch gen6 to use its own cc state boChris Wilson2011-02-211-6/+6
* intel: Buffered uploadChris Wilson2011-02-215-17/+82
* intel: Replace the bo for a complete updateChris Wilson2011-02-211-6/+13
* i965: Combine vb upload buffer with the general upload bufferChris Wilson2011-02-216-97/+71
* intel: Pack dynamic draws togetherChris Wilson2011-02-217-20/+88
* intel: Use system memory for DYNAMIC_DRAW source objectsChris Wilson2011-02-211-20/+31
* i965: Trim the trailing NOOP from 3DSTATE_INDEX_BUFFERChris Wilson2011-02-211-23/+12
* i965: Fallback on encountering a NULL render bufferChris Wilson2011-02-211-0/+5
* dri: Remove the old metaops code which has been superceded by ../common/Eric Anholt2011-02-123-374/+1
* radeon: Remove setup of the old dri/ meta code, which is now unused.Eric Anholt2011-02-123-7/+1
* intel: Remove setup of the old dri/ meta code, which is now unused.Eric Anholt2011-02-122-7/+1
* r300/compiler: Don't erase sources when converting RGB->AlphaTom Stellard2011-02-111-6/+0
* mesa: Optionally build a dricore support library (v3)Christopher James Halse Rogers2011-02-111-7/+5
* mesa: Remove empty header file s_trispan.h.Kenneth Graunke2011-02-105-5/+0
* i915: Force lowering of all types of indirect array accesses in the FSIan Romanick2011-02-101-3/+11
* i915: Calculate partial result to temp register firstIan Romanick2011-02-101-8/+8
* r200: add cast to silence warningBrian Paul2011-02-081-1/+1
* mesa: remove _mesa_create_context_for_api()Brian Paul2011-02-0811-11/+12
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