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* i965/eu: Add codegen support for the Gen9+ render target read message.Francisco Jerez2016-08-253-0/+40
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/eu: Take into account the target cache argument in brw_set_dp_read_message.Francisco Jerez2016-08-252-4/+18
| | | | | | | | | | | brw_set_dp_read_message() was setting the data cache as send message SFID on Gen7+ hardware, ignoring the target cache specified by the caller. Some of the callers were passing a bogus target cache value as argument relying on brw_set_dp_read_message not to take it into account. Fix them too. Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Flip the non-coherent framebuffer fetch extension bit on G45-Gen8 ↵Francisco Jerez2016-08-251-0/+3
| | | | | | | | | | | | | | | | | | | | | hardware. This is not enabled on the original Gen4 part because it lacks surface state tile offsets so it may not be possible to sample from arbitrary non-zero layers of the framebuffer depending on the miptree layout (it should be possible to work around this by allocating a scratch surface and doing the same hack currently used for render targets, but meh...). On Gen9+ even though it should mostly work (feel free to force-enable it in order to compare the coherent and non-coherent paths in terms of performance), there are some corner cases like 1D array layered framebuffers that cannot be handled easily by the non-coherent path because of the incompatible layout in memory of 1D and 2D miptrees (it should be possible to work around this too by doing state-dependent recompiles, but it's hard to care enough since Gen9 has native support for coherent render target reads...) Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Implement glBlendBarrier.Francisco Jerez2016-08-251-0/+20
| | | | | | | | | This is a no-op if the platform supports coherent framebuffer fetch, -- If it doesn't we just need to flush the render cache and invalidate the texture cache in order for previous rendering to be visible to framebuffer fetch. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Upload surface state for non-coherent framebuffer fetch.Francisco Jerez2016-08-253-0/+94
| | | | | | | | This iterates over the list of attached render buffers and binds appropriate surface state structures to the binding table block allocated for shader framebuffer read. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Implement support for overriding the texture target in ↵Francisco Jerez2016-08-251-4/+50
| | | | | | | | | | | | | | | | | | | | | brw_emit_surface_state. This allows the caller to bind a miptree using a texture target other than the one it it was created with. The code should work even if the memory layouts of the specified and original targets don't match, as long as the caller only intends to access a single slice of the miptree structure. This will be exploited by the next commit in order to support non-coherent framebuffer fetch of a single layer of a 3D texture (since some generations lack the minimum array element control for 3D textures bound to the sampler unit), and multiple layers of a 1D array texture (since binding it as an actual 1D array texture would require state-dependent recompiles because the same shader couldn't simultaneously work for 1D and 2D array textures due to the different texel fetch coordinate ordering). Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Massage argument list of brw_emit_surface_state().Francisco Jerez2016-08-251-11/+11
| | | | | | | | | | | | | | | | | | This commit does three different things in a single pass in order to keep the amount of churn low: Remove the for_gather boolean argument which was unused, pass the isl_view argument by value rather than by reference since I'll have to modify it from within the function, and add a target argument to allow callers to bind textures using a target other than the original. The prototype of the function now looks like: void brw_emit_surface_state(struct brw_context *brw, struct intel_mipmap_tree *mt, GLenum target, struct isl_view view, uint32_t mocs, uint32_t *surf_offset, int surf_index, unsigned read_domains, unsigned write_domains); Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add missing has_surface_tile_offset flag to the Gen8+ device info ↵Francisco Jerez2016-08-251-0/+2
| | | | | | | | | structures. This surface state control has been supported by all hardware generations since G45. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Return the correct layout from get_isl_dim_layout for pre-ILK cube ↵Francisco Jerez2016-08-251-2/+5
| | | | | | textures. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Factor out isl_surf_dim/isl_dim_layout calculation into functions.Francisco Jerez2016-08-252-23/+55
| | | | | | | | The logic to calculate the right layout and dimensionality for a given GL texture target is going to be useful elsewhere, factor it out from intel_miptree_get_isl_surf(). Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Resolve color for non-coherent FB fetch at UpdateState time.Francisco Jerez2016-08-251-0/+17
| | | | | | | | | | | | This is required because the sampler unit used to fetch from the framebuffer is unable to interpret non-color-compressed fast-cleared single-sample texture data. Roughly the same limitation applies for surfaces bound to texture or image units, but unlike texture sampling, non-coherent framebuffer fetch is by definition non-coherent with previous rendering, so the brw_render_cache_set_check_flush() call can be omitted except after resolve. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Return whether the miptree was resolved from ↵Francisco Jerez2016-08-252-5/+9
| | | | | | | | | intel_miptree_resolve_color(). This will allow optimizing out the cache flush in some cases when resolving wasn't necessary. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Translate nir_intrinsic_load_output on a fragment output.Francisco Jerez2016-08-251-0/+20
| | | | | | | This gets the non-coherent framebuffer fetch path hooked up to the NIR front-end. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Allocate fragment output temporaries on demand.Francisco Jerez2016-08-251-46/+27
| | | | | | | | | This gets rid of the duplication of logic between nir_setup_outputs() and get_frag_output() by allocating fragment output temporaries lazily whenever get_frag_output() is called. This makes nir_setup_outputs() a no-op for the fragment shader stage. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Rework representation of fragment output locations in NIR.Francisco Jerez2016-08-253-10/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The problem with the current approach is that driver output locations are represented as a linear offset within the nir_outputs array, which makes it rather difficult for the back-end to figure out what color output and index some nir_intrinsic_load/store_output was meant for, because the offset of a given output within the nir_output array is dependent on the type and size of all previously allocated outputs. Instead this defines the driver location of an output to be the pair formed by its GLSL-assigned location and index (I've borrowed the bitfield macros from brw_defines.h in order to represent the pair of integers as a single scalar value that can be assigned to nir_variable_data::driver_location). nir_assign_var_locations is no longer useful for fragment outputs. Because fragment outputs are now allocated independently rather than within the nir_outputs array, the get_frag_output() helper becomes necessary in order to obtain the right temporary register for a given location-index pair. The type_size helper passed to nir_lower_io is now type_size_dvec4 rather than type_size_vec4_times_4 so that output array offsets are provided in terms of whole array elements rather than in terms of scalar components (dvec4 is the largest vector type supported by the GLSL so this will cause all individual fragment outputs to have a size of one regardless of the type). Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Fix undefined signed overflow in INTEL_MASK for bitfields of 31 bits.Francisco Jerez2016-08-251-1/+1
| | | | | | | Most likely we had only ever used this macro on bitfields of less than 31 bits -- That's going to change shortly. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Special-case nir_intrinsic_store_output for the fragment shader.Francisco Jerez2016-08-251-0/+15
| | | | | | | | | | | I'm about to change how fragment shader output locations are represented, so the generic nir_intrinsic_store_output implementation that assumes that outputs are just contiguous elements in the big nir_outputs array won't work anymore. This somewhat simplified implementation of nir_intrinsic_store_output for fragment shaders should be functionally equivalent to the current fall-back one. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Implement non-coherent framebuffer fetch using the sampler unit.Francisco Jerez2016-08-252-0/+94
| | | | | | v2: Memoize sample ID, misc codestyle changes. (Ken) Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Emit interpolation setup if non-coherent framebuffer fetch is in use.Francisco Jerez2016-08-251-1/+2
| | | | | | | | This will be required for the next commit since the non-coherent path makes use of the fragment coordinates implicitly, so they need to be calculated. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Force per-sample dispatch if the shader reads from a multisample FBO.Francisco Jerez2016-08-251-1/+2
| | | | | | | | | The result of a framebuffer fetch from a multisample FBO is inherently per-sample, so the spec requires at least those sections of the shader that depend on the framebuffer fetch result to be executed once per sample. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Allocate space in the binding table for non-coherent FB fetch.Francisco Jerez2016-08-254-7/+16
| | | | | | | | | | | | | | Unfortunately due to the inconsistent meaning of some surface state structure fields, we cannot re-use the same binding table entries for sampling from and rendering into the same set of render buffers, so we need to allocate a separate binding table block specifically for render target reads if the non-coherent path is in use. The slight noise is due to the change of brw_assign_common_binding_table_offsets to return the next available binding table index rather than void. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Add brw_wm_prog_key bit specifying whether FB reads should be coherent.Francisco Jerez2016-08-252-0/+7
| | | | | | | | | | | | | | | | | Some of the following changes in this series are specific to the non-coherent path, so I need some way to tell whether the coherent or non-coherent path is in use. The flag defaults to the value of the gl_extensions::MESA_shader_framebuffer_fetch enable so that it can be overridden easily on hardware that supports both framebuffer fetch extensions in order to test the non-coherent path, like: MESA_EXTENSION_OVERRIDE=-GL_EXT_shader_framebuffer_fetch (Of course trying to force-enable the coherent framebuffer fetch extension on hardware without native support won't work and lead to assertion failures). Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Get rid of fs_visitor::do_dual_src.Francisco Jerez2016-08-253-26/+14
| | | | | | | | | | | | | | This boolean flag was being used for two different things: - To set the brw_wm_prog_data::dual_src_blend flag. Instead we can just set it based on whether the dual_src_output register is valid, which will be the case if the shader writes the secondary blending color. - To decide whether to call emit_single_fb_write() once, or in a loop that would iterate only once, which seems pretty useless. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Respect miptree offsets in intel_readpixels_tiled_memcpy()Chad Versace2016-08-251-17/+4
| | | | | | | | | | | | | | | Respect intel_miptree_slice::x_offset,y_offset and intel_mipmap_tree::offset. All three may be non-zero when glReadPixels is called on an EGLImage created from the non-base slice of a miptree. Patch 2/2 that fixes test 'dEQP-EGL.functional.image.create.gles2_cubemap_*'. Reported-by: Haixia Shi <[email protected]> Diagnosed-by: Haixia Shi <[email protected]> Cc: [email protected] Reviewed-by: Kenneth Graunke <[email protected]> Change-Id: I4b397b27e55a743a7094d29fb0a6a4b6b34352b0
* i965: Fix miptree layout for EGLImage-based renderbuffersChad Versace2016-08-251-0/+13
| | | | | | | | | | | | | | | | | | | | When glEGLImageTargetRenderbufferStorageOES() was given an EGLImage created from the non-base slice of a miptree, intel_image_target_renderbuffer_storage() forgot to apply the intra-tile offsets __DRIimage::tile_x,tile_y to the miptree layout. This patch fixes the problem with a quick hack suitable for cherry-picking. A proper fix requires more thorough plumbing in intel_miptree_create_layout() and brw_tex_layout(). Patch 1/2 that fixes test 'dEQP-EGL.functional.image.create.gles2_cubemap_*'. Reported-by: Haixia Shi <[email protected]> Diagnosed-by: Haixia Shi <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Cc: [email protected] Change-Id: I8a64b0048a1ee9e714ebb3f33fffd8334036450b
* meta: Always do GenerateMipmaps in linear colorspace.Kenneth Graunke2016-08-251-2/+10
| | | | | | | | | | | | When generating mipmaps for sRGB textures, force both decode and encode, so the filtering is done in linear colorspace, regardless of settings. Fixes a WebGL conformance test in Chrome: https://www.khronos.org/registry/webgl/sdk/tests/conformance2/textures/misc/tex-srgb-mipmap.html?webglVersion=2 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97322 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* swrast: fix incorrectly positioned putImage() in swrast driverBrian Paul2016-08-251-2/+2
| | | | | | | | | | | | | | | Some front buffer rendering was in the wrong position. This included scissored clears, glDrawPixels and glCopyPixels. The problem was the y coordinate passed to putImage() didn't match the y coordinate passed to getImage(). We fix this by setting xrb->map_y to the inverted coordinate in swrast_map_renderbuffer() which is used later by the putImage() call. Also pass xrb->map_y to getImage() to be symmetric. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97426 Cc: <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965/fs: Don't consider the stencil output to be a color output.Francisco Jerez2016-08-241-1/+2
| | | | | | | | | This would cause gl_FragStencilRef to be counted as a color output incorrectly during the precompile phase, which leads to unnecessary recompilation on master and could trigger an assertion failure in fs_visitor::emit_fb_writes() on my i965-fb-fetch branch. Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Rename "texturebarrier" source files to "barrier".Francisco Jerez2016-08-241-2/+2
| | | | | | | In preparation for collecting all pipeline barrier GL entry points into a single source file. Reviewed-by: Kenneth Graunke <[email protected]>
* i915: remove unnecessary `if`Eric Engestrom2016-08-241-3/+1
| | | | | | | | | | | if (x) return true; else return false; can be simplified as: return x; since `x` is already a boolean expression. Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965: remove unnecessary `if`Eric Engestrom2016-08-241-6/+2
| | | | | | | | | | | if (x) return true; else return false; can be simplified as: return x; since both `x` are already boolean expressions. Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* dri: add a way to request that modes have matching color/zs depthsIlia Mirkin2016-08-237-12/+27
| | | | | | | | | | Some GPUs, notably nv3x/nv4x can't render to mismatched color/zs framebuffer depths. Fallbacks can be done by the driver, with shadow surfaces, but no reason to encourage applications to select non-matching glx visuals. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* i965/surface_formats: Don't advertise 8 or 16-bit RGB formatsJason Ekstrand2016-08-231-0/+10
| | | | | | | | | | | | | We have implicitly been not advertising these formats since we had them turned off in the format capabilities table. We are about to update that table and this prevents a change in behavior. The only change in behavior created by this patch is that we no longer advertise support for R16G16B16_FLOAT which means that it's now renderable which seems like a bonus. Maybe someday we'll want to change things to start supporting 16-bit RGB formats natively but, at the moment, there's no need. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* i965: report bound buffer size not underlying buffer size for image size (v2)Dave Airlie2016-08-231-2/+2
| | | | | | | | | | | | | | This seems to make sense, the image is bound to a subset of the buffer so the image size should be from the bound size not the underlying object. This fixes: GL44-CTS.shader_image_size.advanced-nonMS-fs-int v2: get mininum of the two values, same as we write to the hw. Reviewed-by: Francisco Jerez <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* i965: use new subroutine index uploader.Dave Airlie2016-08-2311-0/+25
| | | | | | | | This plugs the subroutine index updates into the i965 backend, where it loads constants. Signed-off-by: Dave Airlie <[email protected]> Acked-by: Andres Gomez <[email protected]>
* android: i965: add per-gen libmesa_i965_gen{8,9} staticMauro Rossi2016-08-201-1/+45
| | | | | | | Needed to fix android build after commit 16a9fcb which enabled genxml for gen{8,9} state setup This is the last patch needed, android build tested successfully.
* android: i965: add per-gen libmesa_i965_gen{7,75} static librariesMauro Rossi2016-08-201-1/+45
| | | | | | | | Needed to fix android build after commit e198983 which enabled genxml for gen{7,75} state setup Android build fix for gen{8,9} will follow as incremental patch, build tested successfully with all per-gen patches applied.
* android: i965: add per-gen libmesa_i965_gen6 static libraryMauro Rossi2016-08-201-3/+45
| | | | | | | | Needed to fix android build after commit c8bc1ae where new per-gen genX_blorp.c source replaced gen6_blorp.c for gen6 Android build fixes for gen{7,75} and gen{8,9} will follow as incremental patches, build tested successfully with all per-gen patches applied.
* i965/cfg: Factor common code out of switch statement.Matt Turner2016-08-201-8/+2
| | | | Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965: Remove comment within a comment.Matt Turner2016-08-191-1/+1
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* i965/sched: Simplify work done by add_barrier_deps().Matt Turner2016-08-191-0/+9
| | | | | | | | | | | | | Scheduling barriers are implemented by placing a dependence on every node before and after the barrier. This is unnecessary as we can limit the number of nodes we place dependencies on to those between us and the next barrier in each direction. Runtime of dEQP-GLES31.functional.ssbo.layout.random.all_shared_buffer.23 is reduced from ~25 minutes to a little more than three. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94681 Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vec4: Ignore swizzle of VGRF for use by var_range_end().Matt Turner2016-08-192-2/+2
| | | | | | | | | | | | | | | | | | | | | var_range_end(v, n) loops over the n components of variable number v and finds the maximum value, giving the last use of any component of v. Therefore it expects v to correspond to the variable associated with the .x channel of the VGRF. var_from_reg() however returns the variable for the first channel of the VGRF, post-swizzle. So, if the last register had a swizzle with y, z, or w in the swizzle component, we would read out of bounds. For any other register, we would read liveness information from the next register. The fix is to convert the src_reg to a dst_reg in order to call the dst_reg version of var_from_reg() that doesn't consider the swizzle. Cc: [email protected] Reviewed-by: Francisco Jerez <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vec4: Print spills:fills.Matt Turner2016-08-191-7/+11
| | | | | | | Allows shader-db to work on vec4 programs (has been broken since shader-db commit 646df5ca98b2 from April!) Reviewed-by: Kenneth Graunke <[email protected]>
* nir: Add nir_builder support for individual system value loads.Eric Anholt2016-08-192-5/+3
| | | | | | | | | | The previous nir_load_system_value(b, nir_intrinsic_load_whatever), 0) was rather verbose, when system values should be easy to generate. The index is left out because only one system value had an index included in it. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/blorp: Remove no longer used state setup helpersJason Ekstrand2016-08-193-657/+0
| | | | | | | | Now that we're using genxml for everything, we no longer need the hand-rolled state emit helpers. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Use genxml for gen8-9 state setupJason Ekstrand2016-08-196-587/+172
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Use genxml for gen7 state setupJason Ekstrand2016-08-196-565/+299
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Add genxml-based vertex setup helpersJason Ekstrand2016-08-191-1/+212
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Add a helper for emitting surface statesJason Ekstrand2016-08-191-24/+28
| | | | | | | | The new helper emits surface states and the binding table in one go. It's nice to have it pulled out of the main blorp_exec function. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Add genxml-based sampler state emit functionJason Ekstrand2016-08-191-11/+38
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
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