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path: root/src/mesa/drivers
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* meta: Compute correct buffer size with SkipRows/SkipPixelsChris Wilson2015-09-021-15/+30
* i965/vec4: fill src_reg type using the constructor type parameterAlejandro PiƱeiro2015-09-021-0/+2
* i965: Prevent coordinate overflow in intel_emit_linear_blitChris Wilson2015-09-011-38/+34
* i965/nir: enable the dead control flow optimizationConnor Abbott2015-09-011-0/+2
* i965: advertise ASTC support for SkylakeNanley Chery2015-08-311-0/+5
* i965/fs: Use greater-equal cmod to implement maximum.Matt Turner2015-08-312-4/+6
* i965/chv|skl: Apply sampler bypass w/aBen Widawsky2015-08-312-0/+15
* i965/fs: Remove fs_visitor::try_replace_with_sel().Matt Turner2015-08-283-92/+0
* i965/fs: Replace awful variable names.Matt Turner2015-08-281-40/+40
* i965/fs: Skip blocks in register coalescing interference check.Matt Turner2015-08-281-14/+20
* i965/fs: Improve register coalescing interference check.Matt Turner2015-08-281-8/+11
* i965/fs: Use overwrites_reg() instead of dst.equals().Matt Turner2015-08-281-2/+2
* i965: Only consider fixed_hw_reg in equals() if file is HW_REG/IMM.Matt Turner2015-08-282-3/+6
* i965/fs: Do not set the size for zero-size uniformsMarta Lofstedt2015-08-281-3/+4
* i965/nir: Make use of nir_opt_undefBoyan Ding2015-08-271-0/+2
* i965/fs: Split VGRFs after lowering pull constantsJason Ekstrand2015-08-271-2/+2
* i964/fs: Refactor assign_constant_locationsJason Ekstrand2015-08-271-46/+40
* i965: Rename INTEL_DEBUG=vec4vs to INTEL_DEBUG=vec4.Kenneth Graunke2015-08-271-1/+1
* i965: refactor miptree alignment calculation codeNanley Chery2015-08-261-55/+30
* i965: change the meaning of cpp for compressed texturesNanley Chery2015-08-264-35/+15
* i965: correct mt->align_h for 2D textures on SkylakeNanley Chery2015-08-261-3/+8
* i965: use ALIGN_NPOT for setting ASTC mipmap layoutsNanley Chery2015-08-262-15/+15
* mesa/macros: move ALIGN_NPOT to macros.hNanley Chery2015-08-261-6/+0
* mesa/macros: add power-of-two assertions for alignment macrosNanley Chery2015-08-261-1/+1
* i965/surface_formats: add support for 2D ASTC surface formatsNanley Chery2015-08-262-0/+119
* mesa/formats: remove compressed formats from matching functionNanley Chery2015-08-252-2/+2
* nir: Use nir_shader::stage rather than passing it around.Kenneth Graunke2015-08-251-1/+1
* i965/fs: Combine assign_constant_locations and move_uniform_array_access_to_p...Jason Ekstrand2015-08-252-30/+11
* i965/fs: Rework uniform handlingJason Ekstrand2015-08-253-29/+11
* i965/vec4_nir: Get rid of the uniform_driver_location trackingJason Ekstrand2015-08-252-20/+3
* nir/intrinsics: Add a second const index to load_uniformJason Ekstrand2015-08-252-2/+2
* nir: Pass a type_size() function pointer into nir_lower_io().Kenneth Graunke2015-08-252-18/+11
* i965: Move type_size() methods out of visitor classes.Kenneth Graunke2015-08-258-27/+28
* i965: Make setup_vec4_uniform_value and _image_uniform_values take an offsetJason Ekstrand2015-08-257-22/+38
* i965: Rename setup_vector_uniform_values to setup_vec4_uniform_valueJason Ekstrand2015-08-256-17/+18
* i965: Always re-emit the pipeline select during invariant state emissionChris Wilson2015-08-241-1/+2
* i965/bdw: Fix 3DSTATE_VF_INSTANCING when the edge flag is usedNeil Roberts2015-08-221-2/+13
* i965: Swap the order of the vertex ID and edge flag attributesNeil Roberts2015-08-222-29/+57
* i965: Move control flush into pipelined conditional renderChris Wilson2015-08-222-14/+11
* i965: Use NIR by default for vertex shadersJason Ekstrand2015-08-201-2/+2
* i965: Fix "handle nir_intrinsic_image_size"Martin Peres2015-08-201-4/+3
* i965: enable GL_ARB_shader_image_sizeMartin Peres2015-08-201-0/+1
* i965: handle nir_intrinsic_image_sizeMartin Peres2015-08-201-0/+46
* mesa: Don't lose track of the shader image layer originally specified by the ...Francisco Jerez2015-08-201-2/+2
* mesa: Rename MaxCombinedImageUnitsAndFragmentOutputs to MaxCombinedShaderOutp...Francisco Jerez2015-08-201-1/+1
* i965/bdw: Fix setting the instancing state for the SGVS elementNeil Roberts2015-08-181-1/+1
* util/ra: Make allocating conflict lists optionalJason Ekstrand2015-08-182-2/+2
* i965/reg_allocate: Use make_reg_conflicts_transitiveJason Ekstrand2015-08-182-3/+12
* drirc: Add "Unigine Oil Rush" quirk (allow_glsl_extension_directive_midshader).Richard Yao2015-08-181-0/+2
* i965/gen7: Resolve GCC sign-compare warning.Rhys Kidd2015-08-181-1/+1