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* mesa: IgnoresJakob Bornecrantz2009-08-061-0/+1
* i965: Fix source depth reg setting for FSes reading and writing to depth.Eric Anholt2009-08-053-1/+5
* Merge branch 'mesa_7_5_branch'Brian Paul2009-08-051-0/+5
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| * intel: Fix inverted test for disabling flushing of front buffer output.Brian Paul2009-08-041-1/+1
| * intel: Wait on the last swapbuffers to complete before queuing a new one.Brian Paul2009-08-043-0/+28
* | r200: emit colorpitchDave Airlie2009-08-051-2/+2
* | i965: Fix dangerous warning I let slip in.Eric Anholt2009-08-041-1/+1
* | i965: Respect CondSwizzle in OPCODE_IF.Eric Anholt2009-08-041-1/+21
* | i965: Emit conditional code updates as required for GLSL VS if statements.Eric Anholt2009-08-041-0/+13
* | i965: Don't set pop_count in the reserved MBZ area of IF statements.Eric Anholt2009-08-041-1/+1
* | i965: Print out ELSE and ENDIF src1 arguments like IF does.Eric Anholt2009-08-041-2/+2
* | r200: fix off-by-one errors causing 6th texture unit to not workRoland Scheidegger2009-08-051-2/+2
* | r200: fix compiler warning (unused var)Roland Scheidegger2009-08-051-2/+0
* | radeon: fix miptree comparison breakageRoland Scheidegger2009-08-051-1/+2
* | intel: implement intelCompressedTexSubImage2DRoland Scheidegger2009-08-051-21/+44
* | intel: Add support for EXT_provoking_vertex.Eric Anholt2009-08-0411-24/+131
* | i965: Spell "conditional" correctly.Eric Anholt2009-08-043-16/+16
* | i965: Hook up the disassembler for INTEL_DEBUG={wm,vs}.Eric Anholt2009-08-048-12/+47
* | i965: Initial import of disasm code from intel-gen4asm.Eric Anholt2009-08-041-0/+901
* | i965: warning fixEric Anholt2009-08-041-1/+1
* | i965: Fix RECT shadow sampling by not losing the other texcoords.Eric Anholt2009-08-041-1/+5
* | i965: Assert that the offset in the VBO is below the VBO size.Eric Anholt2009-08-031-0/+14
* | i965: Even if no VS inputs are set, still load some amount of URB as required.Eric Anholt2009-08-031-0/+11
* | i965: Make sure the VS URB size is big enough to fit a VF VUE.Eric Anholt2009-08-031-2/+8
* | i965: Don't emit bad packets when no VBs are referenced.Eric Anholt2009-08-031-0/+22
* | i965: Calculate enabled[] and nr_enabled once and re-use the values.Eric Anholt2009-08-032-29/+18
* | radeon: more fixes for compressed texturesRoland Scheidegger2009-08-042-11/+30
* | radeon: Fix inverted test for disabling flushing of front buffer output.Eric Anholt2009-08-031-1/+1
* | intel: Fix inverted test for disabling flushing of front buffer output.Eric Anholt2009-08-031-1/+1
* | intel: Wait on the last swapbuffers to complete before queuing a new one.Eric Anholt2009-08-033-0/+28
* | r600: add some new r7xx pci idsAlex Deucher2009-08-032-0/+10
* | egl: Replace IsBound by a pointer to the binding.Chia-I Wu2009-08-031-2/+2
* | r600: add some missing pci idsAlex Deucher2009-08-032-0/+4
* | r600: fix the build when RADEON_DEBUG_BO is setAlex Deucher2009-08-031-1/+1
* | r600: fix r600SetTexOffsetAlex Deucher2009-08-033-5/+39
* | r600: handle state emit betterAlex Deucher2009-08-023-8/+16
* | r600: Logic Operations Fixvehemens2009-08-021-5/+37
* | r600: fix regression in texenvAlex Deucher2009-08-023-60/+37
* | r300: Fix a regression on non-KMSNicolai Hähnle2009-08-021-8/+11
* | r600: fix rectangle texturesAlex Deucher2009-08-012-11/+27
* | r300: Fix corner-case of KIL on R300Nicolai Hähnle2009-08-012-51/+60
* | r300: Fix Z buffer re-emit after window resizeNicolai Hähnle2009-08-012-5/+9
* | radeon: fix r100/r200 compressed texture strideRoland Scheidegger2009-07-312-6/+12
* | radeon: s/r300/radeon in shared code error messageRoland Scheidegger2009-07-311-1/+1
* | radeon: Cliprects has to be updated before doing anything with clip rectanglesPauli Nieminen2009-07-311-1/+2
* | radeon: Remove unused variable from context.Pauli Nieminen2009-07-312-3/+0
* | r600: make sure bos are valid before usign thatAlex Deucher2009-07-312-0/+15
* | r600: fix reloc setupAlex Deucher2009-07-311-37/+31
* | r600: remove unused offset_mod stuffAlex Deucher2009-07-316-81/+14
* | r600: ensure we have enough room for full state emitAlex Deucher2009-07-314-12/+5
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