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* i965: Make get_ccs_surf succeed in alloc_auxNanley Chery2018-05-182-10/+11
* mesa: Remove flush_vertices argument from VAO methods.Mathias Fröhlich2018-05-171-18/+14
* i965/blorp: Disable BLORP clear color updatesNanley Chery2018-05-171-2/+4
* i965/blorp: Also skip the fast clear if the clear color differsNanley Chery2018-05-171-4/+3
* i965/clear: Drop a stale comment in fast_clear_depthNanley Chery2018-05-171-4/+0
* i965: Update the indirect buffer in set_clear_colorNanley Chery2018-05-172-37/+13
* i965/clear: Remove an early return in fast_clear_depthNanley Chery2018-05-171-5/+0
* i965: Use set_clear_color for depth miptreesNanley Chery2018-05-173-19/+2
* Revert "i965: Make the miptree clear color setter take a gl_color_union"Nanley Chery2018-05-173-7/+6
* i965/miptree: Unify aux buffer allocationNanley Chery2018-05-172-142/+82
* i965: Prepare to delete intel_miptree_alloc_ccs()Nanley Chery2018-05-173-15/+16
* i965/miptree: Drop the mt param from alloc_aux_bufferNanley Chery2018-05-171-5/+4
* i965/miptree: Drop the alloc_flags param from alloc_aux_bufferNanley Chery2018-05-171-15/+14
* i965/miptree: Drop the name param from alloc_aux_bufferNanley Chery2018-05-171-5/+4
* i965/miptree: Initialize the indirect clear color to zeroNanley Chery2018-05-171-11/+22
* i965/miptree: Add and use a memset option in alloc_aux_bufferNanley Chery2018-05-171-37/+31
* i965/miptree: Zero-initialize CCS_D buffersNanley Chery2018-05-171-6/+4
* i965/miptree: Fix handling of uninitialized MCS buffersNanley Chery2018-05-171-7/+7
* android: change include "cutils/log.h" to "log/log.h" on Android API >=26jenny.q.cao2018-05-141-0/+4
* mesa/vbo/tnl: Move gl_vertex_array related stuff to tnl.Mathias Fröhlich2018-05-101-19/+19
* mesa: Remove Array._DrawArrays.Mathias Fröhlich2018-05-101-2/+2
* i965: Remove the now unused gl_vertex_array.Mathias Fröhlich2018-05-102-11/+0
* i965: Remove the gl_vertex_array indirection.Mathias Fröhlich2018-05-104-40/+31
* i965: Implement all_varyings_in_vbos in terms of Array._DrawVAO.Mathias Fröhlich2018-05-101-15/+2
* i965,anv: Set the CS stall bit on the ISP disable PIPE_CONTROLJason Ekstrand2018-05-091-1/+2
* i965: Shut up unused variable warnings.Kenneth Graunke2018-05-091-6/+7
* i965: require pixel scoreboard stall prior to ISP disableLionel Landwerlin2018-05-091-1/+8
* i965/blorp: Remove a pile of blorp_blit restrictionsJason Ekstrand2018-05-091-30/+33
* i965/blorp: Allow blorp blits for 16x MSAAJason Ekstrand2018-05-091-4/+0
* i965/surface_state: Use an identity swizzle pre-HaswellJason Ekstrand2018-05-091-0/+6
* i965: silence unused variableLionel Landwerlin2018-05-091-1/+0
* mesa: remove hard-coded OpenGL 3.2 compat limitTimothy Arceri2018-05-091-8/+0
* mesa: add GLSLVersionCompat constantTimothy Arceri2018-05-092-0/+7
* i965: Dump validation list on INTEL_DEBUG=bat,submit.Kenneth Graunke2018-05-081-1/+3
* i965/miptree: Remove redundant fields from intel_miptree_aux_bufferJason Ekstrand2018-05-082-37/+7
* i965: Simplify brw_emit_depthbuffer and brw_emit_depth_stencil_hizJason Ekstrand2018-05-081-81/+26
* i965: Move brw_emit_depth_stencil_hiz higher up in the fileJason Ekstrand2018-05-081-50/+40
* i965: Use ISL for emitting depth/stencil/hiz state on gen6+Jason Ekstrand2018-05-089-671/+129
* i965: Use the brw_depthbuffer atom on all gensJason Ekstrand2018-05-084-17/+4
* i965: Always set depth/stencil write enables on gen7+Jason Ekstrand2018-05-082-11/+6
* i965: Re-order depth/stencil/hiz/clear packets to match ISLJason Ekstrand2018-05-083-47/+47
* i965: Re-emit depth/stencil/hiz on BRW_NEW_AUX_STATEJason Ekstrand2018-05-081-1/+2
* i965: Don't leak blorp on Gen4-5.Kenneth Graunke2018-05-071-2/+1
* i965: Set initial kflags on BO creation.Kenneth Graunke2018-05-071-6/+11
* r200: Enable NV_fog_distanceIan Romanick2018-05-041-0/+1
* i965: Enable NV_fog_distanceIan Romanick2018-05-041-0/+1
* i965: Always try to create a logical contextChris Wilson2018-05-031-15/+14
* intel: decoder: limit to the number decoded lines from VBOLionel Landwerlin2018-05-021-0/+1
* i965: Reuse batch decoder infrastructure rather than open coding it.Kenneth Graunke2018-05-023-223/+55
* i965: Allocate shadow batches to explicitly be the BO size.Kenneth Graunke2018-05-021-7/+5
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