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* intel: in intel_context struct use typedef for sarea structTobias Doerffel2009-08-141-1/+1
| | | | | | | | | | | Using drm_i915_sarea_t instead of struct drm_i915_sarea seems to be a common standard now, therefore fix it also in intel_context structure. Additionally this silences a compiler warning: intel_swapbuffers.c: In function `intelFixupVblank': intel_swapbuffers.c:48: warning: initialization from incompatible pointer type Signed-off-by: Tobias Doerffel <[email protected]>
* r600: emit SURFACE_BASE_UPDATE on depth base updates on rv6xxAlex Deucher2009-08-141-0/+8
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* r600: move non-surface related cb state to general stateAlex Deucher2009-08-131-6/+12
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* r600: move non-surface related depth state to general stateAlex Deucher2009-08-131-23/+15
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* mesa: refactor: move _mesa_is_color/depth/stencil_format() helpers to image.cBrian Paul2009-08-131-0/+1
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* i965: fix cube map on IGDNGXiang, Haihao2009-08-131-5/+8
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* Merge branch 'new-frag-attribs'Brian Paul2009-08-121-27/+34
|\ | | | | | | | | | | | | This branch introduces new FRAG_ATTRIB_FACE and FRAG_ATTRIB_PNTC fragment program inputs for GLSL gl_FrontFacing and gl_PointCoord. Before, these attributes were packed with the FOG attribute. That made things complicated elsewhere.
| * mesa: add new FRAG_ATTRIB_FACE and FRAG_ATTRIB_PNTC fragment program inputsBrian Paul2009-07-291-27/+34
| | | | | | | | | | | | | | | | | | | | Previously, the FOGC attribute contained the fragment fog coord, front/back- face flag and the gl_PointCoord.xy values. Now each of those things are separate fragment program attributes. This simplifies quite a few things in Mesa and gallium. Need to test i965 driver and fix up point coord handling in the gallium/draw module...
* | i965: Make the cube mapping RCP use a writemask.Eric Anholt2009-08-121-2/+2
| | | | | | | | Fixes cube mapping since the scalar changes.
* | i965: Allocate destination registers for GLSL TEX instructions contiguously.Eric Anholt2009-08-121-0/+24
| | | | | | | | | | | | This matches brw_wm_pass*.c behavior, and fixes the norsetto shadow demo. Bug #19489
* | i965: drop dead scalar handling in GLSL.Eric Anholt2009-08-122-14/+0
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* | i965: Correct brw_wm_nr_args for WM_DELTAXY and WM_PIXELXY.Eric Anholt2009-08-121-2/+2
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* | i965: Drop GLSL ABS code, which is translated away in brw_wm_fp.Eric Anholt2009-08-121-20/+0
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* | i965: Drop code for emitting OPCODE_SUB, since brw_wm_fp.c makes it an ADD.Eric Anholt2009-08-121-21/+0
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* | i965: Store the dispatch width in the WM compile struct.Eric Anholt2009-08-122-0/+3
| | | | | | | | I'll be using this in merging brw_wm_emit.c and brw_wm_glsl.c
* | i965: Handle scalar result swizzling in shared GLSL/non-GLSL code.Eric Anholt2009-08-125-69/+103
| | | | | | | | | | This is preparation for merging of brw_wm_glsl.c and brw_wm_emit.c, and glsl.c doesn't swizzle channel results around.
* | i965: Flag ARL-using programs as requiring brw_wm_glsl.cEric Anholt2009-08-121-0/+1
| | | | | | | | This doesn't fix the glean testcase, but I guess it provides hope.
* | i965: Remove some unused WM opcode args.Eric Anholt2009-08-121-6/+4
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* | i965: Avoid re-uploading the index buffer when we don't need to.Eric Anholt2009-08-125-16/+55
| | | | | | | | No performance difference proven at 95% confidence with my GLSL demo (n=10).
* | r600: fix warningAlex Deucher2009-08-122-3/+3
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* | r600: state cleanupsAlex Deucher2009-08-124-52/+40
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* | r600: clean up Create/DestroyContextAlex Deucher2009-08-123-15/+6
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* | r200: Prevent TexGenMatrix from leaking when destroying r200 context.Pauli Nieminen2009-08-122-5/+17
| | | | | | | | Signed-off-by: Pauli Nieminen <[email protected]>
* | vbo: Avoid extra validation of DrawElements.Eric Anholt2009-08-123-38/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | This saves mapping the index buffer to get a bounds on the indices that drivers just drop on the floor in the VBO case (cache win), saves a bonus walk of the indices in the CheckArrayBounds case, and other miscellaneous validation. On intel it's a particularly a large win (50-100% in my app) because even though we let the indices stay in both CPU and GPU caches, we still end up waiting for the GPU to be done with the buffer before reading from it. Drivers that want the min/max_index fields must now check index_bounds_valid and use vbo_get_minmax_index before using them.
* | radeon: Minor warnings cleanup.Eric Anholt2009-08-125-7/+16
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* | i965: Use _MaxElement instead of index-calculated min/max for VBO bounds.Eric Anholt2009-08-121-2/+3
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* | radeon: Add protection against recursive DRM locking.Pauli Nieminen2009-08-124-3/+64
| | | | | | | | | | | | | | | | | | | | Reference counting protects DRM lock call from recursive locking that would cause hang. Code also adds optional debugging output for recursive call that is compiled only if NDEBUG is not defined. This code is not 100% thread safe because mesa doesn't include increment and test atomic operation. There is built-in gcc functions but they are only available from gcc 4.2.
* | r600: A shader is bound that exports Z as a float into Red channelCooper Yuan2009-08-122-0/+4
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* | mesa: handle glDrawPixels images which are larger than max rect texture sizeBrian Paul2009-08-111-3/+47
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* | mesa: added _mesa_meta_draw_pixels()Brian Paul2009-08-112-1/+188
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* | mesa: added META_FOG and optimize some meta_begin/end() codeBrian Paul2009-08-112-28/+36
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* | r600: use the drm ioctls for swap and texture uploadAlex Deucher2009-08-112-31/+27
| | | | | | | | NOTE: THIS REQUIRES AN UPDATED DRM!
* | mesa/glapi: regenerated files from gl_API.xmlBrian Paul2009-08-111-15/+59
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* | r600: update num of interp if posizition is usedCooper Yuan2009-08-111-8/+10
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* | intel: use new _mesa_meta_copy_pixels() functionBrian Paul2009-08-101-165/+2
| | | | | | | | glCopyPixels() no longer hits a software fallback when zooming, blending, etc.
* | mesa: save/restore texture matrix in meta codeBrian Paul2009-08-101-1/+20
| | | | | | | | Also, save/restore viewport and texture state in _mesa_meta_copy_pixels()
* | mesa: for meta blit, check max texture size, use glCopyTexSubImage2D() when ↵Brian Paul2009-08-101-2/+27
| | | | | | | | possible
* | mesa: initial meta implementation of glCopyPixels()Brian Paul2009-08-102-0/+166
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* | mesa: remove debug flush callBrian Paul2009-08-101-2/+0
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* | intel: add missing \n to fprintf()Brian Paul2009-08-101-1/+1
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* | intel: use new _mesa_meta_blit_framebuffer() functionBrian Paul2009-08-102-69/+7
| | | | | | | | | | The previous version of framebuffer blit was a quick hack. The new meta version works pretty well.
* | mesa: new driver meta-ops moduleBrian Paul2009-08-102-0/+881
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement glClear() in terms of quad rendering, implement glBlitFramebuffer() in terms of glCopyTexImage2D + textured quad, etc. There have been several places in the drivers where we've implemented meta rendering similar to this. This is an effort to do it in a more portable and more efficient form. The _mesa_meta_begin/end() functions act like glPush/PopAttrib() but are lighter-weight. Plus, _mesa_meta_begin() resets GL state back to default values (texturing off, identity vertex transform, etc) so the meta drawing functions don't have to worry about it. For now only _mesa_mesa_blit_framebuffer() and _mesa_meta_clear() are implemented. glDrawPixels() and glCopyPixels() would be the next candidates.
* | radeon_fbo: switch short to byte for 565Dave Airlie2009-08-101-1/+1
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* | radeon: fix cut-n-paste in alphabits in fbo codeDave Airlie2009-08-101-1/+1
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* | r600: looks like a typoDave Airlie2009-08-091-1/+1
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* | r600: load per-pixel position into PS in order to use fragment.position.Cooper Yuan2009-08-091-0/+27
| | | | | | | | | | This patch can fix /progs/fp/tri-depth, tri-depth2, tri-depthwrite, tri-depthwrite2 and point-position.
* | Revert "i965: Disable texture tiling by default."Eric Anholt2009-08-071-1/+5
| | | | | | | | | | | | | | This reverts commit b8e638d4895d2d342306bb6443a455f73903ce20. Now that the known hangs and misrendering issues are fixed, I'm ready to start encouraging it by default again.
* | intel: Align region height as required for tiled regions.Eric Anholt2009-08-071-0/+5
| | | | | | | | | | | | | | Otherwise, we would address beyond the end of our buffers. Fixes reliable GPU segfault with texture_tiling=true and oglconform shadow.c. Bug #22406.
* | i965: Add a note justifying domain choice for the SF VP.Eric Anholt2009-08-071-0/+3
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* | intel: Add some more safety asserts in the blit code.Eric Anholt2009-08-071-0/+3
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