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* intel: in intel_context struct use typedef for sarea structTobias Doerffel2009-08-141-1/+1
* r600: emit SURFACE_BASE_UPDATE on depth base updates on rv6xxAlex Deucher2009-08-141-0/+8
* r600: move non-surface related cb state to general stateAlex Deucher2009-08-131-6/+12
* r600: move non-surface related depth state to general stateAlex Deucher2009-08-131-23/+15
* mesa: refactor: move _mesa_is_color/depth/stencil_format() helpers to image.cBrian Paul2009-08-131-0/+1
* i965: fix cube map on IGDNGXiang, Haihao2009-08-131-5/+8
* Merge branch 'new-frag-attribs'Brian Paul2009-08-121-27/+34
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| * mesa: add new FRAG_ATTRIB_FACE and FRAG_ATTRIB_PNTC fragment program inputsBrian Paul2009-07-291-27/+34
* | i965: Make the cube mapping RCP use a writemask.Eric Anholt2009-08-121-2/+2
* | i965: Allocate destination registers for GLSL TEX instructions contiguously.Eric Anholt2009-08-121-0/+24
* | i965: drop dead scalar handling in GLSL.Eric Anholt2009-08-122-14/+0
* | i965: Correct brw_wm_nr_args for WM_DELTAXY and WM_PIXELXY.Eric Anholt2009-08-121-2/+2
* | i965: Drop GLSL ABS code, which is translated away in brw_wm_fp.Eric Anholt2009-08-121-20/+0
* | i965: Drop code for emitting OPCODE_SUB, since brw_wm_fp.c makes it an ADD.Eric Anholt2009-08-121-21/+0
* | i965: Store the dispatch width in the WM compile struct.Eric Anholt2009-08-122-0/+3
* | i965: Handle scalar result swizzling in shared GLSL/non-GLSL code.Eric Anholt2009-08-125-69/+103
* | i965: Flag ARL-using programs as requiring brw_wm_glsl.cEric Anholt2009-08-121-0/+1
* | i965: Remove some unused WM opcode args.Eric Anholt2009-08-121-6/+4
* | i965: Avoid re-uploading the index buffer when we don't need to.Eric Anholt2009-08-125-16/+55
* | r600: fix warningAlex Deucher2009-08-122-3/+3
* | r600: state cleanupsAlex Deucher2009-08-124-52/+40
* | r600: clean up Create/DestroyContextAlex Deucher2009-08-123-15/+6
* | r200: Prevent TexGenMatrix from leaking when destroying r200 context.Pauli Nieminen2009-08-122-5/+17
* | vbo: Avoid extra validation of DrawElements.Eric Anholt2009-08-123-38/+23
* | radeon: Minor warnings cleanup.Eric Anholt2009-08-125-7/+16
* | i965: Use _MaxElement instead of index-calculated min/max for VBO bounds.Eric Anholt2009-08-121-2/+3
* | radeon: Add protection against recursive DRM locking.Pauli Nieminen2009-08-124-3/+64
* | r600: A shader is bound that exports Z as a float into Red channelCooper Yuan2009-08-122-0/+4
* | mesa: handle glDrawPixels images which are larger than max rect texture sizeBrian Paul2009-08-111-3/+47
* | mesa: added _mesa_meta_draw_pixels()Brian Paul2009-08-112-1/+188
* | mesa: added META_FOG and optimize some meta_begin/end() codeBrian Paul2009-08-112-28/+36
* | r600: use the drm ioctls for swap and texture uploadAlex Deucher2009-08-112-31/+27
* | mesa/glapi: regenerated files from gl_API.xmlBrian Paul2009-08-111-15/+59
* | r600: update num of interp if posizition is usedCooper Yuan2009-08-111-8/+10
* | intel: use new _mesa_meta_copy_pixels() functionBrian Paul2009-08-101-165/+2
* | mesa: save/restore texture matrix in meta codeBrian Paul2009-08-101-1/+20
* | mesa: for meta blit, check max texture size, use glCopyTexSubImage2D() when p...Brian Paul2009-08-101-2/+27
* | mesa: initial meta implementation of glCopyPixels()Brian Paul2009-08-102-0/+166
* | mesa: remove debug flush callBrian Paul2009-08-101-2/+0
* | intel: add missing \n to fprintf()Brian Paul2009-08-101-1/+1
* | intel: use new _mesa_meta_blit_framebuffer() functionBrian Paul2009-08-102-69/+7
* | mesa: new driver meta-ops moduleBrian Paul2009-08-102-0/+881
* | radeon_fbo: switch short to byte for 565Dave Airlie2009-08-101-1/+1
* | radeon: fix cut-n-paste in alphabits in fbo codeDave Airlie2009-08-101-1/+1
* | r600: looks like a typoDave Airlie2009-08-091-1/+1
* | r600: load per-pixel position into PS in order to use fragment.position.Cooper Yuan2009-08-091-0/+27
* | Revert "i965: Disable texture tiling by default."Eric Anholt2009-08-071-1/+5
* | intel: Align region height as required for tiled regions.Eric Anholt2009-08-071-0/+5
* | i965: Add a note justifying domain choice for the SF VP.Eric Anholt2009-08-071-0/+3
* | intel: Add some more safety asserts in the blit code.Eric Anholt2009-08-071-0/+3
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