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* i915: Fix leak of ViewportMatrix data on context destroy.John2011-07-071-0/+2
* intel: Remove gratuitous context checks in intel_delete_renderbuffer().Eric Anholt2011-07-071-14/+5
* intel: Remove now trivial intel_renderbuffer_set_{hiz_,}region().Eric Anholt2011-07-073-57/+19
* intel: Rely on intel_region_reference()'s support of *dst != NULL.Eric Anholt2011-07-074-18/+0
* intel: Allow intel_region_reference() with *dst != NULL.Eric Anholt2011-07-071-4/+6
* intel: Mark MESA_FORMAT_X8_Z24 as always supported.Eric Anholt2011-07-071-1/+1
* i965: Remove unused structures for command packets.Kenneth Graunke2011-07-071-433/+0
* i965: Convert system instruction pointer to OUT_BATCH style.Kenneth Graunke2011-07-072-14/+5
* i965: Convert PIPELINE_SELECT to OUT_BATCH style.Kenneth Graunke2011-07-071-10/+4
* i965: Emit 3DSTATE_VF_STATISTICS in OUT_BATCH style.Kenneth Graunke2011-07-072-18/+4
* i965: Convert 3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP to OUT_BATCH style.Kenneth Graunke2011-07-072-19/+5
* i965/fs: Fix message register allocation in FB writes.Kenneth Graunke2011-07-061-5/+6
* i965/fs: Implement new ir_unop_u2i and ir_unop_i2u opcodes.Kenneth Graunke2011-06-292-0/+10
* i965/gen7: Add missing ! to brw->gs.prog_active assertion.Kenneth Graunke2011-06-291-1/+1
* i965: Reissue PIPELINE_POINTERS and BINDING_TABLE_POINTERS on SBA change.Eric Anholt2011-06-286-12/+55
* i965/gen6: Fix scissors using invalid STATE_BASE_ADDRESS.Eric Anholt2011-06-281-2/+2
* i965: step message register allocationBen Widawsky2011-06-271-5/+5
* Revert "Fix 24bpp software rendering"Brian Paul2011-06-253-89/+4
* i965/gen5: Fix grf_used calculation for 16-wide.Eric Anholt2011-06-241-5/+4
* i965: fix mask used to write to clip distance registers when gen>6Paul Berry2011-06-241-1/+1
* intel: Fix workaround for _mesa_update_framebufferChad Versace2011-06-241-3/+5
* intel: Change framebuffer validation criteriaChad Versace2011-06-241-10/+3
* intel: In intel_update_wrapper, support s8z24 textures when using separate st...Chad Versace2011-06-241-6/+35
* intel: Factor region updates out of intel_update_wrapperChad Versace2011-06-241-0/+18
* intel: During glTexImage, allocate renderbuffers for faking s8z24 texturesChad Versace2011-06-241-0/+62
* intel: Declare some functions in intel_fbo.c as non-staticChad Versace2011-06-242-2/+14
* intel: Change signature of intel_create_wrapped_renderbufferChad Versace2011-06-242-22/+12
* intel: Perform gather on s8z24 texture images during glGetTexImageChad Versace2011-06-241-0/+8
* intel: Define functions intel_texture_s8z24_scatter/gatherChad Versace2011-06-241-0/+70
* intel: Add fields to intel_texture for faking s8z24 with separate stencilChad Versace2011-06-243-12/+40
* i965: Make the brw_format_for_mesa_format table static const.Eric Anholt2011-06-241-1/+1
* i965: Don't bother telling swrast_setup about state updates until fallback.Eric Anholt2011-06-243-1/+4
* i965: Don't bother telling tnl about state updates unless we fall back.Eric Anholt2011-06-244-2/+18
* i965: Reuse existing program data when a new compiled program matches.Eric Anholt2011-06-242-20/+82
* Fix 24bpp software renderingMarc Pignat2011-06-243-4/+89
* dri/r200: properly spell current_atom.Stéphane Marchesin2011-06-231-1/+1
* dri/r200: rename __atom to current_atom.Stéphane Marchesin2011-06-231-3/+3
* i965/gen6: Add a couple more packets to the nonpipelined workaround list.Eric Anholt2011-06-231-0/+6
* intel: Implement DRIimageExtension::dupImageBenjamin Franzke2011-06-231-1/+26
* r600c: add missing bank tiling case for evergreenAlex Deucher2011-06-221-0/+3
* r600c: use BASE_VTX_LOC & AUTO_INDEX for drawing nonindexed with offsetAndre Maasikas2011-06-221-60/+8
* intel: Allocate s8_z24 non-texture renderbuffers when using separate stencilChad Versace2011-06-211-3/+81
* intel: Unobfuscate intel_alloc_renderbuffer_storageChad Versace2011-06-211-17/+17
* intel: Add fields to intel_renderbuffer for unwrapping packed depth/stencil b...Chad Versace2011-06-214-44/+118
* intel: Unconditionally enable support for S8_Z24 texture formatChad Versace2011-06-211-1/+1
* i965/gen6: Apply documented workaround for nonpipelined state packets.Eric Anholt2011-06-203-1/+45
* i965/gen6: Limit the workaround flush to once per primitive.Eric Anholt2011-06-205-0/+16
* i965/gen6: Use an BO instead of writing to address 0 for PIPE_CONTROL W/A.Eric Anholt2011-06-204-3/+23
* i965/gen6: Factor the PIPE_CONTROL workaround to a separate function.Eric Anholt2011-06-201-8/+21
* i965/gen6: Remove state flagging on BRW_NEW_CURBE_OFFSETS.Eric Anholt2011-06-203-6/+3
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