summaryrefslogtreecommitdiffstats
path: root/src/mesa/drivers
Commit message (Collapse)AuthorAgeFilesLines
* intel: Fix software detiling of system stencil buffersChad Versace2011-11-152-4/+6
| | | | | | | | | | | | | | | | | | | | If a window system stencil buffer had a region with odd height, then the calculated y offset needed for software detiling was off by one. The bug existed in intel_{map,unmap}_renderbuffer_s8() and in the intel_span.c accessors. Fixes the following Piglit tests on gen7: general/depthstencil-default_fb-readpixels-24_8 general/depthstencil-default_fb-readpixels-FLOAT-and-USHORT Fixes SIGABRT in the following Piglit tests on gen7: general/depthstencil-default_fb-blit general/depthstencil-default_fb-copypixels general/depthstencil-default_fb-drawpixels-24_8 general/depthstencil-default_fb-drawpixels-FLOAT-and-USHORT Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* intel: Fix intel_unmap_renderbuffer_s8()Chad Versace2011-11-151-2/+2
| | | | | | | | | | | | | | | | | | When gathering the temporary buffer's pixles into the gem buffer, we had the two buffers juxtaposed. Oops. Fixes the following Piglit tests on gen7: general/GL_SELECT - alpha-test enabled general/GL_SELECT - depth-test enabled general/GL_SELECT - no test function general/GL_SELECT - scissor-test enabled general/GL_SELECT - stencil-test enabled Fixes SIGABRT in Piglit tests EXT_framebuffer_object/fbo-stencil-* on gen7. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* intel: Refactor intel_map_renderbuffer()Chad Versace2011-11-151-134/+256
| | | | | | | | | | | The function already implements 3 cases (map through GTT, blit to a temporary, and detile stencil buffer to temporary), and a 4th will be added soon: scatter/gather for depthstencil buffers using separate stencil. For sanity's sake, this factors each case out into its own function. Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* meta: Fix restoring of fixed function texture enables.Eric Anholt2011-11-141-27/+9
| | | | | | | | | | | | | If they were disabled on entry, and we enabled one (like for BlitFramebuffer), we wouldn't disable it on the way out. Retain the attempted optimization here (don't keep calling to set each bit for changes that won't matter) by just setting the bits directly with appropriate flushing. Fixes misrendering on the second draw of piglit fbo-blit. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* meta: Don't forget to flag state when restoring texobjects.Eric Anholt2011-11-141-2/+5
| | | | | | | It's unlikely that we changed the object but no other texture parameter, but be correct anyway. Noticed by inspection. Reviewed-by: Ian Romanick <[email protected]>
* radeon: further cleanup of shared codeFabio Pedretti2011-11-143-23/+6
| | | | Signed-off-by: Alex Deucher <[email protected]>
* radeon: add some missing FireMV pci idsAlex Deucher2011-11-141-0/+1
| | | | | | Note: this is a candidate for the stable branches. Signed-off-by: Alex Deucher <[email protected]>
* i965: Don't try to normalize cubemap coordinates for textureSize.Kenneth Graunke2011-11-121-0/+3
| | | | | | | | | | Although textureSize is represented as an ir_texture with op == ir_txs, it doesn't have a coordinate, so normalizing it doesn't make sense. Fixes crashes in oglconform glsl-bif-tex-size basic.samplerCube.* tests. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Expose GLSL 1.30 on gen6+.Eric Anholt2011-11-111-1/+4
| | | | | | | With the gl_VertexID support, everything required should now be supported. Reviewed-by: Ian Romanick <[email protected]>
* i965: Add support for gl_VertexID and gl_InstanceID.Eric Anholt2011-11-114-6/+63
| | | | | | | | | | | | | The compiler setup for these VF-uploaded attributes looks a little cheesy with mixing system values and real VBO-sourced attributes. It would be nice if we could just compute the ATTR[] map to GRF index up front and use it at visit time instead of using ir->location in the ATTR file. However, we don't know the reg_offset at visit(ir_variable *) time, so we can't do the mapping that early. Fixes piglit vertexid test. Reviewed-by: Ian Romanick <[email protected]>
* i965: Replace a should-never-happen fallback with asserts where it matters.Eric Anholt2011-11-112-13/+15
| | | | | | | | | | | | We only allow 16 vec4s of attributes in our GLSL/ARB_vp programs, and 1 more element will get used for gl_VertexID/gl_InstanceID. So it should never have been possible to hit this fallback, unless there was another bug. If you do hit this, you're probably using gl_VertexID and falling back to swrast won't work for you anyway. This also updates the limits for gen6+. Reviewed-by: Ian Romanick <[email protected]>
* radeon: fix build.Dave Airlie2011-11-111-1/+1
| | | | | | I had a later patch remove this code, but cherry-picked across it. Signed-off-by: Dave Airlie <[email protected]>
* radeon: drop unused constant_cliprect fieldDave Airlie2011-11-112-2/+0
|
* radeon: disable texobj state for 3d textureDave Airlie2011-11-111-0/+1
| | | | | | for 3d texture fallback, disable the texobj state. Signed-off-by : Dave Airlie <[email protected]>
* radeon: use meta bitmapDave Airlie2011-11-111-0/+1
| | | | | | Now that the stride bug is fixed, enable Bitmap via meta mode. Signed-off-by: Dave Airlie <[email protected]>
* radeon: fix bug with wrong stride being used for rectangluar textures.Dave Airlie2011-11-114-6/+6
| | | | | | This broke the meta bitmap code when it was enabled. Signed-off-by: Dave Airlie <[email protected]>
* i965: remove #include of api_noop.hBrian Paul2011-11-111-1/+0
|
* xlib: set alpha to 0xff when mapping RGB pixmapsBrian Paul2011-11-111-0/+11
| | | | Fixes a bunch of conform regressions.
* i965: Make Gen6+ renderbuffer surface updates not depend on NEW_COLOR.Kenneth Graunke2011-11-103-2/+12
| | | | | | | | | | NEW_COLOR is only needed on Gen4-5 as brw_update_renderbuffer_surfaces only uses ctx->Color when intel->gen < 6. This should reduce unnecessary state updates. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Reorder state atom lists so all the surface state is together.Kenneth Graunke2011-11-101-16/+19
| | | | | | | Not strictly necessary, but seems like a good idea. Suggested-by: Eric Anholt <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Put a proper sampler count in 3DSTATE_VS.Kenneth Graunke2011-11-102-3/+5
| | | | | | | See similar code for 3DSTATE_WM. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Upload SAMPLER_STATE pointers for the VS on Ivybridge.Kenneth Graunke2011-11-101-1/+7
| | | | | | | See similar code in gen7_wm_state.c. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Move and rename "wm sampler" fields to just "sampler".Kenneth Graunke2011-11-109-33/+37
| | | | | | | | | | | | | brw_wm_samplers actually enables any active samplers regardless of what pipeline stage is using them, so it doesn't make much sense for it to be WM-specific. So, rename it to "brw_samplers." To properly generalize it, move sampler_count and sampler_offset from brw_context::wm to a new brw_context::sampler that can be shared without looking strange. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Clean up code for VS pull constant surface creation.Kenneth Graunke2011-11-103-64/+20
| | | | | | | | | | Like for the WM pull constants, we can merge the former prepare/emit stages into one tracked state atom. Furthermore, the code that used to handle the binding table was removed in the last commit, leaving some rather silly looking short functions that can easily be folded in. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Use a single binding table for all pipeline stages.Kenneth Graunke2011-11-109-85/+80
| | | | | | | | | | | | | | | | | | | | | | | Although the hardware supports separate binding tables for each pipeline stage, we don't see much advantage over a single shared table. Consider the contents of the binding table: - Textures (16) - Draw buffers (8) - Pull constant buffers (1 for VS, 1 for WM) OpenGL's texture bindings are global: the same set of textures is available to all shader targets. So our binding table entries for textures would be exactly the same in every table. There are only two pull constant buffers (not many), and although draw buffers aren't interesting to the VS, it shouldn't hurt to have them in the table. The hardware supports up to 254 binding table entries, and we currently only use 26. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Split brw_wm_surfaces state into renderbuffer and texture atoms.Kenneth Graunke2011-11-103-15/+35
| | | | | | | | | | | | | First, the texturing setup code is relevant for all pipeline stages, while renderbuffer surfaces are only used by the WM. Secondly, renderbuffer and texture setup depends on a different set of dirty bits. There's no reason to walk the array of textures when changing draw buffers, or vice-versa. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Combine the two WM pull constant tracked state atoms.Kenneth Graunke2011-11-104-59/+16
| | | | | | | | | | | | | | | | These were only split for historical reasons: brw_wm_constants used to be the "prepare" step, while brw_wm_constant_surface was "emit". Now that both happen at emit time, it makes sense to combine them. Call the newly combined state atom "brw_wm_pull_constants" to indicate help distinguish it from the Gen6+ atoms that handle push constants. Finally, remove the BRW_NEW_WM_CONSTBUF dirty bit entirely now that it's never flagged nor used. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Rename gen6_*_constants tracked state atoms to "push_constants".Kenneth Graunke2011-11-104-8/+8
| | | | | | | | | | | | | | | When reading the "brw_wm_constants" and "gen6_wm_constants" atoms side-by-side, I initially failed to notice the crucial difference: the Gen6 atoms are for Push Constants, while brw_wm_constants handles Pull Constants. (Gen4/5 Push Constants are handled by "brw_curbe.") Renaming these should clarify the code and save me from constant confusion over the fact that "gen6_wm_constants" isn't just a newer version of "brw_wm_constants." Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Remove nr_surfaces computation from brw_update_wm_surfaces.Kenneth Graunke2011-11-101-11/+1
| | | | | | | | | | | | This code is fairly fragile, as it depends on the ordering of the entries in the binding table, which will change soon. Also, stop listening on the BRW_NEW_WM_CONSTBUF dirty bit as it's no longer required. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Use 0 for the number of binding table entries in 3DSTATE_(VS|WM).Kenneth Graunke2011-11-1010-50/+6
| | | | | | | | | | | | | | | | | | | | | | These fields control how many entries the hardware prefetches into the state cache, so they only impact performance, not correctness. However, it's not clear how to use this in a way that's beneficial. According to the documentation, kernels "using a large number" of entries may wish to program this to zero to avoid thrashing the cache; it's unclear how many is too many. Also, Ironlake's WM was missing this feature entirely---the count had to be zero. The dirty bit tracking to handle this complicates the surface state and binding table setup; removing it should simplify things and make future refactoring easier. So just set 0 for the number of entries rather than trying to compute and track it. Appears to have no impact on Nexuiz and OpenArena on Sandybridge. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Remove outdated comment about CACHE_NEW_SURF_BIND dirty bit.Kenneth Graunke2011-11-101-2/+1
| | | | | | | | | | The comment states that brw_update_vs_constant_surface produces a CACHE_NEW_SURF_BIND dirty bit, but it doesn't. In fact, that bit no longer even exists. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Remove BRW_NEW_NR_VS_SURFACES dirty bit from brw_vs_surfaces.Kenneth Graunke2011-11-101-1/+0
| | | | | | | | | | | | | | | brw_vs_surfaces _produces_ the BRW_NEW_NR_VS_SURFACES dirty bit, so it makes no sense for it to subscribe to it. Fixes an assertion failure in many piglit tests when INTEL_DEBUG is set: brw_state_upload.c:484: void brw_upload_state(struct brw_context *): Assertion `!check_state(&examined, &generated)' failed. One such piglit test is vs-uniform-array-mat2-col-rd.shader_test. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Add missing CACHE_NEW_WM_PROG dirty bit to WM pull constants.Kenneth Graunke2011-11-101-2/+3
| | | | | | | | | | | | | Comparing brw_upload_vs_pull_constants and brw_upload_wm_pull_constants, it became evident that something was amiss: the VS code had both CACHE_NEW_VS_PROG and BRW_NEW_VERTEX_PROGRAM, while the WM code was missing the CACHE_NEW_WM_PROG flag. Not observed to fix anything, but likely necessary. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Use new vtable entries for surface state updating functions.Kenneth Graunke2011-11-104-126/+13
| | | | | | | | | | Now that we have vtable entries in place, we should use them. This allows us to drop the cut and pasted Gen7 brw_tracked_state atoms as they now do exactly the same thing as their brw_wm_surface_state counterparts. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Add new vtable entries for surface state updating functions.Kenneth Graunke2011-11-105-0/+49
| | | | | | | | | | | | | | | Gen7+ SURFACE_STATE is different from Gen4-6, so we need separate per-generation functions for creating and updating it. However, the usage is the same, and callers just want to utilize the appropriate functions with minimal pain. So, put them in the vtable. Since these take a brw_context pointer and are only used on Gen4, just add a forward declaration. This is the simplest (if not cleanest) solution. It would be nicer to have a i965-specific vtable, but that's a refactor for another day. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* radeon: silence unused var warningsBrian Paul2011-11-101-3/+3
|
* radeon: fix tex1d-border2dDave Airlie2011-11-101-31/+33
| | | | | | Fixes pigit test with T wrap usage. Signed-off-by: Dave Airlie <[email protected]>
* radeon: fix 3-coordinate swtcl emissionDave Airlie2011-11-101-0/+8
| | | | | | This fixes mipmap generation on swtcl rv100. Signed-off-by: Dave Airlie <[email protected]>
* meta: Add support for glClear() to integer color buffers.Eric Anholt2011-11-091-4/+109
| | | | | | | | | | This requires using a new fragment shader to get the integer color output, and a new vertex shader because #version has to match between the two. v2: Clarify that there's no need for BindFragDataLocation. Reviewed-by: Kenneth Graunke <[email protected]> (v1)
* i965: Claim to support rendering to integer FBOs.Eric Anholt2011-11-092-1/+13
| | | | | | | | | | | | We're missing support for the software paths still, but basic rendering is working. v2: Override RGB_INT32/UINT32 to not be renderable, since the hardware can't do it but we do allow texturing from it now. Drop the DataType override, since the _mesa_problem() isn't in that path any more. Reviewed-by: Kenneth Graunke <[email protected]> (v1)
* i965/fs: Add support for user-defined out variables.Eric Anholt2011-11-092-35/+39
| | | | | | | | | | | | Before, I was tracking the ir_variable * found for gl_FragColor or gl_FragData[]. Instead, when visiting those variables, set up an array of per-render-target fs_regs to copy the output data from. This cleans up the color emit path, while making handling of multiple user-defined out variables easier. v2: incorporate idr's feedback about ir->location (changes by Kenneth Graunke) Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Preserve the source register type when doing color writes.Eric Anholt2011-11-091-4/+7
| | | | | | | When rendering to integer color buffers, we need to be careful to use MRFs of the correct type when emitting color writes. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Make brw_type_for_base_type return the element type for arrays.Eric Anholt2011-11-091-0/+1
| | | | | | | | | | | | | | | | Previously, brw_type_for_base_type returned UD for array variables, similar to structures. For structures, each field may have a different type, so every field access must explicitly override the register's type with that field's type. We chose to return UD in this case since it was the least common, so errors would be more obvious. For arrays, it makes far more sense to return the type corresponding to an element of the array. This allows normal array access to work without the hassle of explicitly overriding the register's type. This should obsolete a bunch of type overrides throughout the code. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Enable ChooseTexFormat for supported GL_EXT_texture_integer formats.Eric Anholt2011-11-091-0/+30
| | | | | | | v2: s/GL_TRUE/true/, and re-enable RGB_INT32 based on discussion yesterday about required RB formats vs texture formats. Reviewed-by: Kenneth Graunke <[email protected]> (v1)
* i965: Add mapping from MESA_FORMAT to BRW_SURFACEFORMAT for integer.Eric Anholt2011-11-091-0/+24
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Expose GL_EXT_texture_integer when GL 3.0 override is set.Eric Anholt2011-11-091-0/+10
| | | | | | | This will let the feature be incrementally developed, hidden behind the flag we're all using as we work on GL 3.0 support. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add support for 16-bit unorm L, A, and I textures.Eric Anholt2011-11-092-1/+8
| | | | | | | | | | | | While not required by any particular spec version, mplayer was asking for L16 and hoping for actual L16 without checking. The 8 bits allocated led to 10-bit planar video data stored in the lower 10 bits giving only 2 bits of precision in video. While it was an amusing effect, give them what they actually wanted instead. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=41461 Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Don't _mesa_problem when asked for an RB of a texturing-only type.Eric Anholt2011-11-092-2/+11
| | | | | | | | We want to be able to support some formats for texturing that we can't render to, which means that some choices for RenderbufferStorage end up being incomplete (for example, L8 currently). For these, where we don't render to them, we don't want to have to make up an rb->DataType that's only used for GetRow()/PutRow().
* r200: remove dangling radeon.h symlink.Paul Berry2011-11-091-1/+0
| | | | | | | | | | | | Commit 1401b96b (radeon: cleanup radeon shared code after r300 and r600 classic drivers removal) removed the file src/mesa/drivers/dri/radeon/server/radeon.h, but it left behind the symlink which was used to share that file into the src/mesa/drivers/dri/r200/server directory. This patch removes the dangling symlink. Reviewed-by: Alex Deucher <[email protected]>
* i965: Move _mesa_ir_link_shader call before device-specific linkingIan Romanick2011-11-071-3/+3
| | | | | | | | | | | | | | | _mesa_ir_link_shader needs to be called before cloning the IR tree so that the var->location field for uniforms is set. WARNING: This change breaks several integer division related piglit tests. The tests break because _mesa_ir_link_shader lowers integer division to an RCP followed by a MUL. The fix is to factor out more of the code from ir_to_mesa so that _mesa_ir_link_shader does not need to be called at all by the i965 driver. This will be the subject of several follow-on patches. Signed-off-by: Ian Romanick <[email protected]> Tested-by: Tom Stellard <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-28 08:23:31 +0000