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* intel: Take advantage of GL_READ_ONLY_ARB to map to GEM bo_map write flag.Eric Anholt2009-04-232-5/+4
* intel: fix max anisotropy supportedRoland Scheidegger2009-04-225-3/+7
* i965: const correctnessBrian Paul2009-04-211-49/+49
* r300: r300 hw doesn't support any input modifiers in tex instsMaciej Cencora2009-04-211-2/+1
* gdi: Don't implement broken gl_dispatch_stub_xxx.José Fonseca2009-04-201-77/+0
* r300: fix register-negate branch merge regressionMaciej Cencora2009-04-203-39/+12
* i965: use region width, height in brw_update_renderbuffer_surface()Brian Paul2009-04-181-2/+2
* intel: #include polygon.h to silence warningBrian Paul2009-04-181-0/+1
* intel: Handle ARB_vertex_buffer_object state in intel_clear_tris().Michel Dänzer2009-04-181-0/+5
* intel: make sure polygon mode is set properly in intel_clear_tris()Brian Paul2009-04-171-0/+2
* i915: fix broken indirect constant buffer readsBrian Paul2009-04-173-51/+40
* dri: __driUtilMessage(): not all messages are errorsBrian Paul2009-04-171-1/+1
* i965: updated CURBE allocation codeBrian Paul2009-04-173-8/+15
* Merge branch 'register-negate'Brian Paul2009-04-1614-109/+93
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| * mesa: merge the prog_src_register::NegateBase and NegateAbs fieldsBrian Paul2009-04-1414-109/+93
* | i915: Remove dead i830TexEnv and i915TexEnv.Eric Anholt2009-04-165-182/+0
* | intel: Add support for argb1555, argb4444 FBOs and fix rgb565 fbo readpixels.Eric Anholt2009-04-169-125/+346
* | i965: disable using immediate values for MOV instructionsBrian Paul2009-04-161-1/+3
* | i965: minor debug output changesBrian Paul2009-04-161-3/+3
* | i965: const buffer debug code (disabled)Brian Paul2009-04-161-0/+12
* | i965: implement relative addressing for VS constant buffer readsBrian Paul2009-04-163-59/+115
* | i965: handle address reg in get_dst()Brian Paul2009-04-161-0/+4
* | i965: fix const buffer temp register clobberingBrian Paul2009-04-161-7/+18
* | intel: fix small compressed texture uploadRoland Scheidegger2009-04-161-4/+5
* | i965: Clean up output of WM SS state dump, and add format output.Eric Anholt2009-04-151-3/+17
* | i915: Use DEBUG_WM (like 965) for printing the fragment program out.Eric Anholt2009-04-151-4/+2
* | i915: Add decode of dest buffer variables (destination format)Eric Anholt2009-04-151-0/+30
* | intel: Fix segfault when doing SW mipmap generation with a PBO texture upload.Eric Anholt2009-04-151-3/+10
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* i965: fix VS constant buffer readsBrian Paul2009-04-143-35/+25
* DRI2: Don't fault on NULL DrawBufferIan Romanick2009-04-141-1/+1
* i965: checkpoint commit: VS constant buffersBrian Paul2009-04-1411-91/+477
* dri glx: Swap before checking for cliprects.Younes Manton2009-04-131-3/+3
* i965: remove unused varBrian Paul2009-04-101-1/+0
* i965: clean-up in prepare_wm_surfaces()Brian Paul2009-04-101-8/+4
* mesa: reduce makefile outputBrian Paul2009-04-101-4/+5
* i965: added null const_buffer pointer check in update_constant_buffer()Brian Paul2009-04-101-1/+1
* intel: added screen->dri2.loader null pointer check in intel_flush()Brian Paul2009-04-101-1/+2
* i965: re-org of some of the new constant buffer codeBrian Paul2009-04-094-48/+81
* i965: new SURF_INDEX_ macrosBrian Paul2009-04-095-40/+49
* intel / DRI2: Accept fake front-buffer from loaderIan Romanick2009-04-091-0/+5
* intel / DRI2: Track and flush front-buffer renderingIan Romanick2009-04-093-0/+46
* i965: free shader's constant buffer in brwDeleteProgram()Brian Paul2009-04-091-0/+6
* i965: set BRW_MASK_DISABLE flag in "send" instruction in brw_dp_READ_4()Brian Paul2009-04-081-1/+2
* i965: clean-ups, debug code in brw_wm_glsl.cBrian Paul2009-04-081-34/+15
* i965: init current_const[i].index = -1Brian Paul2009-04-081-3/+4
* i965: move the fetch_constants() call before setting conditional mod stateBrian Paul2009-04-081-4/+4
* intel: Avoid dri2 GetBuffers round-trips for internal Viewport calls.Eric Anholt2009-04-063-3/+10
* i965: Use GTT maps when available to upload vertex arrays and system VBOs.Eric Anholt2009-04-063-18/+55
* intel: Clean up some a leftover from sedding of bufmgr context->screen move.Eric Anholt2009-04-061-3/+0
* radeon: Expose a 32 bit RGBA fbconfig even when the screen depth is 16.Michel Dänzer2009-04-061-15/+20
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