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* dri_util: fail driCreateNewScreen if InitScreen is NULLPaulo Zanoni2011-01-131-0/+3
| | | | | | | | | Without this, X doesn't start with UMS on r300g. NOTE: This is a candidate for the 7.9 and 7.10 branches. Signed-off-by: Paulo Zanoni <[email protected]> Signed-off-by: Brian Paul <[email protected]>
* i965/fs: Do flat shading when appropriate.Eric Anholt2011-01-122-20/+42
| | | | | We were trying to interpolate, which would end up doing unnecessary math, and doing so on undefined values. Fixes glsl-fs-flat-color.
* meta: Actually use mipmapping when generating mipmaps.Eric Anholt2011-01-121-1/+1
| | | | | | | | With the change to not reset baselevel, this GL_LINEAR filtering was resulting in generating mipmaps off of the base level instead of the next higher detail level. Fixes fbo-generatemipmap-filtering. Reported by: Neil Roberts <[email protected]>
* i965: Clarify when we need to (re-)calculate live intervals.Eric Anholt2011-01-123-5/+27
| | | | | | The ad-hoc placement of recalculation somewhere between when they got invalidated and when they were next needed was confusing. This should clarify what's going on here.
* i965/vs: When MOVing to produce ABS, strip negate of the operand.Eric Anholt2011-01-121-0/+1
| | | | | We were returning the negative absolute value, instead of the absolute value. Fixes glsl-vs-abs-neg.
* i965/fs: When producing ir_unop_abs of an operand, strip negate.Eric Anholt2011-01-121-0/+1
| | | | | We were returning the negative absolute value, instead of the absolute value. Fixes glsl-fs-abs-neg.
* i965: Tighten up the check for flow control interfering with coalescing.Eric Anholt2011-01-111-12/+26
| | | | | | This greatly improves codegen for programs with flow control by allowing coalescing for all instructions at the top level, not just ones that follow the last flow control in the program.
* i965: Remove dead fallback for stencil _Enabled but no stencil buffer.Eric Anholt2011-01-111-8/+0
| | | | | The _Enabled field is the thing that takes into account whether there's a stencil buffer. Tested with piglit glx-visuals-stencil.
* r600c: add evergreen ARL support.Alberto Milone2011-01-111-14/+69
| | | | Signed-off-by: Alberto Milone <[email protected]>
* i965: Use a new miptree to avoid software fallbacks due to drawing offset.Eric Anholt2011-01-102-40/+67
| | | | | | | | | When attaching a small mipmap level to an FBO, the original gen4 didn't have the bits to support rendering to it. Instead of falling back, just blit it to a new little miptree just for it, and let it get revalidated into the stack later just like any other new teximage. Bug #30365.
* intel: Drop the speculatively-use-firstImage-mt in validation.Eric Anholt2011-01-101-17/+0
| | | | | It's been replaced by just setting texObj->mt to image->mt at TexImage time.
* intel: Don't relayout the texture on maxlevel change.Eric Anholt2011-01-101-7/+6
| | | | | | | This avoids relayouts in the common case of glGenerateMipmap() or people doing similar things. Bug #30366.
* intel: When making a new teximage miptree, make a full one.Eric Anholt2011-01-101-79/+68
| | | | | | | | If we hit this path, we're level 1+ and the base level got allocated as a single level instead of a full tree (so we don't match intelObj->mt). This tries to recover from that so that we end up with 2 allocations and 1 validation blit (old -> new) instead of allocations equal to number of levels and levels - 1 blits.
* meta: Don't tweak BaseLevel when doing glGenerateMipmap().Eric Anholt2011-01-101-4/+1
| | | | | | | We don't need to worry about levels other than MaxLevel because we're minifying -- the lower levels (higher detail) won't contribute to the result. By changing BaseLevel, we forced hardware that doesn't support BaseLevel != 0 to relayout the texture object.
* Revert "intel: Always allocate miptrees from level 0, not tObj->BaseLevel."Eric Anholt2011-01-1010-82/+152
| | | | | | | | | | | This reverts commit 7ce6517f3ac41bf770ab39aba4509d4f535ef663. This reverts commit d60145d06d999c5c76000499e6fa9351e11d17fa. I was wrong about which generations supported baselevel adjustment -- it's just gen4, nothing earlier. This meant that i915 would have never used the mag filter when baselevel != 0. Not a severe bug, but not an intentional regression. I think we can fix the performance issue another way.
* i965: Add #defines for HiZ and separate stencil buffer commands.Kenneth Graunke2011-01-101-0/+3
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* i965: Add new HiZ related bits to WM_STATE.Kenneth Graunke2011-01-101-1/+8
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* i965: Rename more #defines to 3DSTATE rather than CMD or CMD_3D.Kenneth Graunke2011-01-103-22/+22
| | | | Again, this makes it match the documentation.
* i965: Remove unused #defines which only contain the sub-opcode.Kenneth Graunke2011-01-101-22/+0
| | | | | | | | | Most _3DSTATE defines contain the command type, sub-type, opcode, and sub-opcode (i.e. 0x7905). These, however, contain only the sub-opcode (i.e. 0x05). Since they are inconsistent with the rest of the code and nothing uses them, simply delete them. The _3DOP and _3DCONTROL defines seemed similar, and were also unused.
* r600: Include mfeatures.h in files that perform feature tests.Vinson Lee2011-01-092-0/+2
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* r300: Include mfeatures.h in files that perform feature tests.Vinson Lee2011-01-092-0/+2
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* r200: Include mfeatures.h in files that perform feature tests.Vinson Lee2011-01-092-0/+2
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* radeon: Include mfeatures.h in files that perform feature tests.Vinson Lee2011-01-095-0/+5
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* dri/nouveau: Include mfeatures.h in files that perform feature tests.Vinson Lee2011-01-092-0/+3
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* intel: Include mfeatures.h in files that perform feature tests.Vinson Lee2011-01-096-0/+7
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* intel: Make renderbuffer tiling choice match texture tiling choice.Eric Anholt2011-01-071-4/+9
| | | | | | There really shouldn't be any difference between the two for us. Fixes a bug where Z16 renderbuffers would be untiled on gen6, likely leading to hangs.
* intel: Use the _BaseFormat from MESA_FORMAT_* in renderbuffer setup.Eric Anholt2011-01-071-36/+1
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* i915: Drop old checks for the settexoffset hack.Eric Anholt2011-01-072-17/+6
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* i915: Don't claim to support AL1616 when neither 830 nor 915 does it.Eric Anholt2011-01-071-1/+2
| | | | Fixes an abort in fbo-generatemipmap-formats.
* intel: Add a vtbl hook for determining if a format is renderable.Eric Anholt2011-01-077-38/+68
| | | | | | | By relying on just intel_span_supports_format, some formats that aren't supported pre-gen4 were not reporting FBO incomplete. And we also complained in stderr when it happened on i915 because draw_region gets called before framebuffer completeness validation.
* intel: expose ARB_framebuffer_object in the i915 driver.Eric Anholt2011-01-071-1/+1
| | | | | | | | | | | ARB_fbo no longer disallows mismatched width/height on attachments (shouldn't be any problem), mixed format color attachments (we only support 1), and L/A/LA/I color attachments (we already reject them on 965 too). It requires Gen'ed names (driver doesn't care), and adds FramebufferTextureLayer (we don't do texture arrays). So it looks like we're already in the position we need to be for this extension. Bug #27468, #32381.
* i965: Avoid double-negation of immediate values in the VS.Eric Anholt2011-01-071-4/+3
| | | | | | | | | | | | | | In general, we have to negate in immediate values we pass in because the src1 negate field in the register description is in the bits3 slot that the 32-bit value is loaded into, so it's ignored by the hardware. However, the src0 negate field is in bits1, so after we'd negated the immediate value loaded in, it would also get negated through the register description. This broke this VP instruction in the position calculation in civ4: MAD TEMP[1], TEMP[1], CONST[256].zzzz, CONST[256].-y-y-y-y; Bug #30156
* r600c: fix up SQ setup in blit code for Ontario/NIAlex Deucher2011-01-071-1/+87
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* r600c: add support for NI asicsAlex Deucher2011-01-065-1/+118
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* i965: Rename various gen6 #defines to match the documentation.Kenneth Graunke2011-01-0612-33/+33
| | | | | | | | This should make it easier to cross-reference the code and hardware documentation, as well as clear up any confusion on whether constants like CMD_3D_WM_STATE mean WM_STATE (pre-gen6) or 3DSTATE_WM (gen6+). This does not rename any pre-gen6 defines.
* mesa: fix build for NetBSDPierre Allegraud2011-01-061-3/+3
| | | | | | | | See http://bugs.freedesktop.org/show_bug.cgi?id=32859 NOTE: This is a candidate for the 7.9 and 7.10 branches. Signed-off-by: Brian Paul <[email protected]>
* i965: skip too small size mipmapZou Nan hai2011-01-061-2/+4
| | | | this fixes doom3 crash.
* i915: Fix build for previous commit.Eric Anholt2011-01-051-11/+11
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* intel: Always allocate miptrees from level 0, not tObj->BaseLevel.Eric Anholt2011-01-059-141/+71
| | | | | | | | | | | BaseLevel/MaxLevel are mostly used for two things: clamping texture access for FBO rendering, and limiting the used mipmap levels when incrementally loading textures. By restricting our mipmap trees to just the current BaseLevel/MaxLevel, we caused reallocation thrashing in the common case, for a theoretical win if someone really did want just levels 2..4 or whatever of their texture object. Bug #30366
* intel: Drop unused first/lastlevel args to miptree_create_for_region.Eric Anholt2011-01-053-8/+3
| | | | We're always making a single-level, 0-baselevel miptree.
* intel: Clarify first_level/last_level vs baselevel/maxlevel by deletion.Eric Anholt2011-01-057-56/+30
| | | | | | | | | This has always been ugly about our texture code -- object base/max level vs intel object first/last level vs image level vs miptree first/last level. We now get rid of intelObj->first_level which is just tObj->BaseLevel, and make intelObj->_MaxLevel clearly based off of tObj->_MaxLevel instead of duplicating its code (incorrectly, as image->MaxLog2 only considers width/height and not depth!)
* i915: Enable LOD preclamping on 8xx like on 915/965.Eric Anholt2011-01-052-0/+3
| | | | Fixes lodclamp-between and lodclamp-between-max.
* i915: Implement min/max lod clamping in hardware on 8xx.Eric Anholt2011-01-053-25/+32
| | | | | This avoids 8xx-specific texture relayout for min/max lod changes. One step closer to avoiding relayout for base/maxlevel changes!
* intel: Drop TEXTURE_RECTANGLE check in miptree layout setup.Eric Anholt2011-01-051-37/+24
| | | | | It's already handled by our non-mipmapped MinFilter, since TEXTURE_RECTANGLE is always NEAREST or LINEAR.
* intel: Clean up redundant setup of firstLevel.Eric Anholt2011-01-051-5/+4
| | | | | It's always BaseLevel (since TEXTURE_RECTANGLE's baselevel can't be changed from 0), except for 8xx minlod hilarity.
* intel: Drop a check for GL_TEXTURE_4D_SGIS.Eric Anholt2011-01-051-1/+0
| | | | | The SGIS_texture4D extension was thankfully never completed, so we couldn't implement it if we wanted to.
* i965: Simplify the renderbuffer setup code.Eric Anholt2011-01-051-102/+93
| | | | | | It was quite a mess by trying to do NULL renderbuffers and real renderbuffers in the same function. This clarifies the common case of real renderbuffers.
* i965: use BLT to clear buffer if possible on SandybridgeXiang, Haihao2011-01-051-6/+0
| | | | This fixes https://bugs.freedesktop.org/show_bug.cgi?id=32713
* i965: Add support for SRGB DXT1 formats.Eric Anholt2011-01-043-2/+10
| | | | | | | | | | This makes fbo-generatemipmap-formats GL_EXT_texture_sRGB-s3tc match fbo-generatemipmap-formats GL_EXT_texture_compression_s3tc and swrast in bad DXT1_RGBA alpha=0 handling, but it means we won't unpack and repack someone's textures into uncompressed SARGB8 format.
* intel: Merge our choosetexformat fallbacks into core.Eric Anholt2011-01-045-229/+60
| | | | | | We now share the type/format -> MESA_FORMAT_* mappings with software mesa, and the core supports most of the fallbacks hardware drivers will want.
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