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path: root/src/mesa/drivers
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* intel: Deassociated drawables from private context struct in intelUnbindContextIan Romanick2009-09-161-0/+8
* intel: add B43 chipset supportZhenyu Wang2009-09-102-1/+6
* i965: fix incorrect test for vertex position attributeBrian Paul2009-09-083-1/+4
* i965: Fix warnings in intel_pixel_read.c.Eric Anholt2009-09-041-0/+4
* intel: Also get the DRI2 front buffer when doing front buffer reading.Eric Anholt2009-09-044-1/+29
* intel: Update Mesa state before span setup in glReadPixels.Eric Anholt2009-09-043-3/+13
* intel: Move intel_pixel_read.c to shared for use with i965.Eric Anholt2009-09-042-306/+307
* i965: Add missing state dependency of sf_unit on _NEW_BUFFERS.Eric Anholt2009-09-041-2/+4
* intel: Align cubemap texture height to its padding requirements.Eric Anholt2009-09-041-0/+10
* intel: Align untiled region height to 2 according to 965 docs.Eric Anholt2009-09-041-0/+7
* i965: Fix source depth reg setting for FSes reading and writing to depth.Eric Anholt2009-09-043-1/+5
* i965: Respect CondSwizzle in OPCODE_IF.Eric Anholt2009-09-041-1/+21
* i965: asst clean-ups, etc in brw_vs_emit()Brian Paul2009-09-041-11/+10
* i965: Emit conditional code updates as required for GLSL VS if statements.Eric Anholt2009-09-041-0/+13
* i965: Spell "conditional" correctly.Eric Anholt2009-09-043-15/+15
* i965: Fix RECT shadow sampling by not losing the other texcoords.Eric Anholt2009-09-041-1/+5
* i965: Assert that the offset in the VBO is below the VBO size.Eric Anholt2009-09-041-0/+14
* i965: Even if no VS inputs are set, still load some amount of URB as required.Eric Anholt2009-09-041-0/+11
* i965: Make sure the VS URB size is big enough to fit a VF VUE.Eric Anholt2009-09-041-1/+8
* i965: Don't emit bad packets when no VBs are referenced.Eric Anholt2009-09-041-0/+22
* i965: Calculate enabled[] and nr_enabled once and re-use the values.Eric Anholt2009-09-042-29/+18
* i965: Set the max index buffer address correctly according to the docs.Eric Anholt2009-09-041-1/+1
* i965: rename var: s/tmp/vs_inputs/Brian Paul2009-09-041-8/+8
* dri: Fix problems with unitialized values in dri screen object.Pauli Nieminen2009-08-071-1/+1
* intel: Fix inverted test for disabling flushing of front buffer output.Brian Paul2009-08-041-1/+1
* intel: Wait on the last swapbuffers to complete before queuing a new one.Brian Paul2009-08-043-0/+28
* intel: Fix leak of DRI option info due to using the wrong free routine.Brian Paul2009-07-271-1/+1
* intel: Clean up leak of driver context structure on context destroy.Brian Paul2009-07-271-0/+3
* intel: Use _mesa_warning() to report GEM warningsBrian Paul2009-07-271-3/+3
* windows: updated VC8 project filesKarl Schultz2009-07-271-1/+0
* intel: Fall back on glBitmap with fog enabled.Eric Anholt2009-07-201-0/+6
* i965: Don't clip everything if FRONT_AND_BACK culling while culling disabled.Eric Anholt2009-07-201-1/+2
* radeon: With DRI1, if we have HW stencil, only expose fbconfigs with stencil.Michel Dänzer2009-07-201-2/+2
* r128: fix two-sided lighting segfault seen in GLUT's olight demoPeteri Andras2009-07-133-2/+7
* intel: Bump driver data, add RC3 tagintel_2009q2_rc3Ian Romanick2009-07-121-1/+1
* i965: fix fetching constants from constant buffer in glsl pathRoland Scheidegger2009-07-044-17/+16
* i965: Remove bad constant buffer constant-reg-already-loaded optimization.Eric Anholt2009-07-041-13/+11
* intel: Also update stencil bits in intel_update_wrapper().Michel Dänzer2009-07-031-0/+1
* i915: Fix assertion failure on remapping a non-BO-backed VBO.Eric Anholt2009-06-301-1/+4
* intel: added null ptr checkBrian Paul2009-06-291-1/+1
* intel / DRI2: Additional flush of fake front-buffer to real front-bufferIan Romanick2009-06-261-0/+11
* i965: handle OPCODE_SWZ in the glsl pathRoland Scheidegger2009-06-221-0/+1
* intel: intel_texture_drawpixels() can't handle GL_DEPTH_STENCIL.Michel Dänzer2009-06-221-1/+1
* i965: added intelFlush() call in intel_get_tex_image()Brian Paul2009-06-221-0/+6
* intel: Fix other metaops versus GL_COMPILE_AND_EXECUTE dlists.Eric Anholt2009-06-192-3/+3
* intel: Fix glClear behavior versus display lists.Eric Anholt2009-06-191-1/+1
* radeons: use dp4 for position invariant vertex programsRoland Scheidegger2009-06-193-0/+6
* intel: remove extra \n from warning stringBrian Paul2009-06-171-1/+1
* i965: fix 1D texture borders with GL_CLAMP_TO_BORDERRobert Ellison2009-06-171-0/+10
* i965: send all warnings through _mesa_warning()Robert Ellison2009-06-171-1/+1
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