summaryrefslogtreecommitdiffstats
path: root/src/mesa/drivers
Commit message (Collapse)AuthorAgeFilesLines
* i965/msaa: Set KILL_ENABLE when GL_ALPHA_TO_COVERAGE enabled.Paul Berry2012-06-262-4/+6
| | | | | | | | | | | | | | | i965 hardware needs to be informed of situations in which it's possible for pixels (or samples) to be discarded for reasons other than depth/stencil testing (e.g. due to an explicit "discard" in the fragment shader). One of these situations is when GL_ALPHA_TO_COVERAGE is enabled, since that can cause samples to be discarded by the color calculator when the pixel's alpha value is less than 1.0. Without this patch, GL_ALPHA_TO_COVERAGE does not take effect on depth buffers. Reviewed-by: Anuj Phogat <[email protected]>
* i965/msaa: Implement GL_SAMPLE_ALPHA_TO_{COVERAGE,ONE}.Paul Berry2012-06-261-1/+9
| | | | | | | | | | | | | | | | | | | | | | This patch enables the multisampling parameters GL_SAMPLE_ALPHA_TO_COVERAGE and GL_SAMPLE_ALPHA_TO_ONE, which allow the fragment shader's alpha output to be converted into a sample coverage mask and ignored for blending. i965 supports these parameters through the BLEND_STATE structure. The GL spec allows, but does not require, the implementation to dither the conversion from alpha to a sample coverage mask, so that alpha values that aren't a multiple of 1/num_samples result in the correct proportion of samples being lit. A bit exists in the BLEND_STATE structure to enable this functionality, but according to the hardware docs it must be disabled on Sandy Bridge (see the Sandy Bridge PRM, Vol2, Part1, p379: AlphaToCoverage Dither Enable). So it is enabled for Gen7 only. Fixes piglit tests "EXT_framebuffer_multisample/sample-alpha-to-{coverage,one} {2,4}". Reviewed-by: Anuj Phogat <[email protected]>
* i965/msaa: Implement glSampleCoverage.Paul Berry2012-06-264-7/+26
| | | | | | | | | | | | | | This patch enables glSampleCoverage() functionality, which allows the client program to specify that only a portion of the samples be lit up when performing multisampled rendering. i965 supports glSampleCoverage() through the 3DSTATE_SAMPLE_MASK command packet, which allows the driver to specify a bitfield indicating which samples to light up. Fixes piglit tests "EXT_framebuffer_multisample/sample-coverage {2,4} {inverted,non-inverted}". Reviewed-by: Anuj Phogat <[email protected]>
* i965/fs: Fix conversions float->bool, int->boolChad Versace2012-06-251-7/+7
| | | | | | | | | | | | | | | | | Fixes gles2conform GL.equal.equal_bvec2_frag. This fixes brw_fs_visitor's translation of ir_unop_f2b. It used CMP to convert the float to one of 0 or ~0. However, the convention in the compiler is that true is represented by 1, not ~0. This patch adds an AND to convert ~0 to 1. By inspection, a similar problem existed with ir_unop_i2b, with a similar fix. [v2 kayden]: eliminate extra temporary register. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=49621 Signed-off-by: Chad Versace <[email protected]>
* i965/msaa: Add backend support for centroid interpolation.Paul Berry2012-06-253-11/+32
| | | | | | | | | | | | | | | This patch causes the fragment shader to be configured correctly (and the correct code to be generated) for centroid interpolation. This required two changes: brw_compute_barycentric_interp_modes() needs to determine when centroid barycentric coordinates need to be included in the pixel shader thread payload, and fs_visitor::emit_general_interpolation() needs to interpolate using the correct set of barycentric coordinates. Fixes piglit tests "EXT_framebuffer_multisample/interpolation {2,4} centroid-edges" on i965. Reviewed-by: Eric Anholt <[email protected]>
* i965/fs: Refactor interpolation code to prepare for adding centroid support.Paul Berry2012-06-252-8/+17
| | | | Reviewed-by: Eric Anholt <[email protected]>
* i965/msaa: Adapt clip setup for centroid noperspective interpolation.Paul Berry2012-06-253-2/+6
| | | | | | | | | | | | | | | | | | To save time, we only instruct the clip stage of the pipeline to compute noperspective barycentric coordinates if those coordinates are needed by the fragment shader. Previously, we would determine whether the coordinates were needed by seeing whether the fragment shader used the BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC interpolation mode. However, with MSAA, it's possible that the fragment shader might use BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC instead. In the future, when we support ARB_sample_shading, it might use BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC. This patch modifies the upload_clip_state() functions to check for all three possible noperspective interpolation modes. Reviewed-by: Eric Anholt <[email protected]>
* i965: Compute dFdy() correctly for FBOs.Paul Berry2012-06-226-9/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On i965, dFdx() and dFdy() are computed by taking advantage of the fact that each consecutive set of 4 pixels dispatched to the fragment shader always constitutes a contiguous 2x2 block of pixels in a fixed arrangement known as a "sub-span". So we calculate dFdx() by taking the difference between the values computed for the left and right halves of the sub-span, and we calculate dFdy() by taking the difference between the values computed for the top and bottom halves of the sub-span. However, there's a subtlety when FBOs are in use: since FBOs use a coordinate system where the origin is at the upper left, and window system framebuffers use a coordinate system where the origin is at the lower left, the computation of dFdy() needs to be negated for FBOs. This patch modifies the fragment shader back-ends to negate the value of dFdy() when an FBO is in use. It also modifies the code that populates the program key (brw_wm_populate_key() and brw_fs_precompile()) so that they always record in the program key whether we are rendering to an FBO or to a window system framebuffer; this ensures that the fragment shader will get recompiled when switching between FBO and non-FBO use. This will result in unnecessary recompiles of fragment shaders that don't use dFdy(). To fix that, we will need to adapt the GLSL and NV_fragment_program front-ends to record whether or not a given shader uses dFdy(). I plan to implement this in a future patch series; I've left FIXME comments in the code as a reminder. Fixes Piglit test "fbo-deriv". NOTE: This is a candidate for stable release branches. Reviewed-by: Kenneth Graunke <[email protected]>
* automake: Convert src/mesa/drivers/x11/Makefile to automake.Eric Anholt2012-06-213-81/+75
| | | | | | | | | The weird versioning of the libGL where the package version was sort of expressed as a big integer is dropped. libtool didn't like the 0 prefix, and it didn't really make sense anyway -- if you interpret it as an integer version number, old Mesa 071200 was bigger than current Mesa 08100. Instead, just bump the minor version and drop the patchlevel.
* automake: Convert src/mesa/drivers/Makefile to automake.Eric Anholt2012-06-213-29/+23
|
* make: Fold ASM_CFLAGS into DEFINES.Eric Anholt2012-06-217-7/+0
| | | | | | Every place that uses ASM_FLAGS already uses DEFINES. Not including it in DEFINES is just a way to screw up potential users, as I've done several times while working on the build system.
* i965/msaa: Only do multisample rasterization if GL_MULTISAMPLE enabled.Paul Berry2012-06-204-18/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | From the GL 3.0 spec (p.116): "Multisample rasterization is enabled or disabled by calling Enable or Disable with the symbolic constant MULTISAMPLE." Elsewhere in the spec, where multisample rasterization is described (sections 3.4.3, 3.5.4, and 3.6.6), the following text is consistently used: "If MULTISAMPLE is enabled, and the value of SAMPLE_BUFFERS is one, then..." So, in other words, disabling GL_MULTISAMPLE should prevent multisample rasterization from occurring, even if the draw framebuffer is multisampled. This patch implements that behaviour by setting the WM and SF stage's "multisample rasterization mode" to MSRAST_ON_PATTERN only when the draw framebuffer is multisampled *and* GL_MULTISAMPLE is enabled. Fixes piglit test spec/EXT_framebuffer_multisample/enable-flag. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/msaa: Disable unsupported formats.Paul Berry2012-06-201-0/+13
| | | | | | | | | | | | | | | | | | | | | | | Due to hardware limitations, MSAA is unsupported on Gen6 for formats containing >64 bits of data per pixel. From the Sandy Bridge PRM, vol4 part1, p72 ("Surface Format"): If Number of Multisamples is set to a value other than MULTISAMPLECOUNT_1, this field cannot be set to the following formats: - any format with greater than 64 bits per element - any compressed texture format (BC*) - any YCRCB* format Gen7 has a similar, but less stringent limitation: formats with >64 bits of data per pixel only support 4x MSAA. This patch causes the unsupported formats to report GL_FRAMEBUFFER_UNSUPPORTED. Fixes piglit "multisample-formats" tests on Gen6. Acked-by: Kenneth Graunke <[email protected]>
* i965: Don't set brw_wm_prog_key::iz_lookup on Gen6+.Kenneth Graunke2012-06-191-18/+20
| | | | | | | | Sandy Bridge and later don't use this field, so there's no point in setting it. It can only cause harmful state-based recompiles. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Fix brw_swap_cmod() for LE/GE comparisons.Kenneth Graunke2012-06-181-4/+4
| | | | | | | | | | | | | | | | | | | | | The idea here is to rewrite comparisons like 2 >= x with x <= 2; we want to simply exchange arguments, not negate the condition. If equality was part of the original comparison, it should remain part of the swapped version. This is the true cause of bug #50298. It didn't manifest itself on Sandybridge because we embed the conditional modifier in the IF instruction rather than emitting a CMP. All other platforms use CMP. It also didn't manifest itself on the master branch because commit be5f27a84d ("glsl: Refine the loop instruction counting.") papered over the problem. NOTE: This is a candidate for stable release branches. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=50298 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Add support for ir_unop_f2u to i965 backend.Paul Berry2012-06-153-0/+3
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/blorp: Implement source clipping.Paul Berry2012-06-151-3/+11
| | | | | | | | | | | | | | | | | This patch modifies blorp blits (which are used for MSAA) to properly account for clipping of source coordinates. Previously, if we detected the possibility of source clipping, we would fall back to the blit meta-op, which doesn't support MSAA and is very slow for depth and stencil buffers. Fixes piglit tests "EXT_framebuffer_multisample/clip-and-scissor-blit" on i965/Gen6+. Also substantially speeds up the Humble Bundle V game "Psychonauts" on Gen6+ (without this patch, the game's depth buffer blits use the slow blit meta-op). Reviewed-by: Carl Worth <[email protected]>
* windows/gdi: Remove GL_NV_register_combiners and GL_NV_vertex_array_range ↵José Fonseca2012-06-141-15/+0
| | | | exports
* meta: Cleanup the resources we allocate.Antoine Labour2012-06-121-6/+66
| | | | | | | | | | | When we have multiple shared contexts, and one of them is long-running, this will lead to never freeing those resources since they are shared. Instead, free them right away on context destruction since we know the other context isn't using them. Reviewed-by: Ian Romanick <[email protected]> NOTE: This is a candidate for the 8.0 branch.
* i965: Add forgotten bitcast operations in brw_fs_channel_expressions.Kenneth Graunke2012-06-071-0/+4
| | | | Signed-off-by: Kenneth Graunke <[email protected]>
* i965/blorp: allow all buffer formats provided src and dst match.Paul Berry2012-06-071-25/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, blits using the "blorp" mechanism only worked for 8-bit RGBA color buffers, 24-bit depth buffers, and 8 bit stencil buffers. This was not enough, because the blorp mechanism must be used for blitting whenever MSAA is in use. This patch allows all formats to be used, provided the source and destination formats match. So far I have confirmed that the following formats work properly with MSAA: - GL_RGB - GL_RGBA - GL_ALPHA - GL_ALPHA4 - GL_ALPHA8 - GL_R3_G3_B2 - GL_RGB4 - GL_RGB5 - GL_RGB8 - GL_RGB10 - GL_RGB12 - GL_RGB16 - GL_RGBA2 - GL_RGBA4 - GL_RGB5_A1 - GL_RGBA8 - GL_RGB10_A2 - GL_RGBA12 - GL_RGBA16 Fixes piglit tests "EXT_framebuffer_multisample/formats {2,4}" on Sandy Bridge and Ivy Bridge. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/blorp: Implement logic for additional buffer formats.Paul Berry2012-06-073-7/+37
| | | | | | | | | | | | | Previously the blorp engine only supported RGBA8 color buffers and 24-bit depth buffers. This patch adds support for any color buffer format that is supported as a render target, and for 16-bit and 32-bit depth buffers. This required threading the brw_context struct through into brw_blorp_surface_info::set() so that it can consult the brw->render_target_format array. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/blorp: De-virtualize brw_blorp_{mip,surface}_info::set() function.Paul Berry2012-06-071-4/+4
| | | | | | | | | | Even though brw_blorp_surface_info is derived from brw_blorp_mip_info, this function doesn't need to be virtual, because it is never accessed through a base class pointer. Making the function non-virtual will allow it to take additional parameters in the brw_blorp_surface_info case. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/blorp: Refactor surface format determination.Paul Berry2012-06-074-10/+10
| | | | | | | | | | | This patch moves the responsibility for deciding on the format of the source and destination surfaces from the gen{6,7}_blorp_emit_surface_state() functions to brw_blorp_surface_info::set(), which is shared between Gen6 and Gen7. This will make it possible to add support for more surface formats without code duplication. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Enable the GL_ARB_shader_bit_encode extension.Kenneth Graunke2012-06-073-0/+25
| | | | Signed-off-by: Kenneth Graunke <[email protected]>
* mesa: consolidate internal glCompressedTexSubImage1/2/3D codeBrian Paul2012-06-062-9/+7
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: consolidate internal glCompressedTexImage1/2/3D codeBrian Paul2012-06-062-6/+4
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: consolidate internal glCopyTexSubImage1/2/3D codeBrian Paul2012-06-067-116/+42
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: consolidate internal glTexSubImage1/2/3D codeBrian Paul2012-06-064-67/+29
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: consolidate internal glTexImage1/2/3D codeBrian Paul2012-06-064-125/+23
| | | | | | | The functions for handling 1D, 2D and 3D texture images were nearly identical. This folds them all together. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Fix user-defined FS outputs with less than four components.Kenneth Graunke2012-06-052-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OpenGL allows you to declare user-defined fragment shader outputs with less than four components: out ivec2 color; This makes sense if you're rendering to an RG format render target. Previously, we assumed that all color outputs had four components (like the built-in gl_FragColor/gl_FragData variables). This caused us to call emit_color_write for invalid indices, incrementing the output virtual GRF's reg_offset beyond the size of the register. This caused cascading failures: split_virtual_grfs would allocate new size-1 registers based on the virtual GRF size, but then proceed to rewrite the out-of-bounds accesses assuming that it had allocated enough new (contiguously numbered) registers. This resulted in instructions that accessed size-1 GRFs which register numbers beyond virtual_grf_next (i.e. registers that were never allocated). Finally, this manifested as live variable analysis and instruction scheduling accessing their temporary array with an out of bounds index (as they're all sized based on virtual_grf_next), and the program would segfault. It looks like the hardware's Render Target Write message requires you to send four components, even for RT formats such as RG or RGB. This patch continues to use all four MRFs, but doesn't bother to fill any data for the last few, which should be unused. +2 oglconforms. NOTE: This is a candidate for stable release branches. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965/vs: Fix texelFetchOffset() on pre-Gen7.Kenneth Graunke2012-06-051-2/+2
| | | | | | | | | | | Commit 4650aea7a536ddce120576fadb91845076e8e37a fixed texelFetchOffset() on Ivybridge, but didn't update the Ironlake/Sandybridge code. +18 piglits on Sandybridge. NOTE: This and 4650aea7a536ddce are both candidates for stable branches. Signed-off-by: Kenneth Graunke <[email protected]>
* i965/fs: Fix texelFetchOffset() on pre-Gen7.Kenneth Graunke2012-06-051-12/+28
| | | | | | | | | | | Commit f41ecade7b458c02d504158b522acb2231585040 fixed texelFetchOffset() on Ivybridge, but didn't update the Ironlake/Sandybridge code. +15 piglits on Sandybridge. NOTE: This and f41ecade7b458 are both candidates for stable branches. Signed-off-by: Kenneth Graunke <[email protected]>
* meta: Fix GL_RENDERBUFFER binding in decompress_texture_image().Kenneth Graunke2012-06-051-0/+4
| | | | | | | | | | | | | This isn't saved/restored by _mesa_meta_begin, so we need to do it manually (like we do for the read/draw framebuffers). Additionally, we neglected to re-bind before the glRenderbufferStorage call. +13 oglconforms. NOTE: This is a candidate for stable release branches. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* i965: Implement texture buffer objects on Gen6.Kenneth Graunke2012-06-022-0/+61
| | | | | | | | | | | Commit a07cf3397e332388d3599c83e50ac45511972890 added support for TBOs on Gen7, but missed Gen6. Passes piglit -t texture_buffer and oglconform's buffermapping basic.read.texture tests. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* intel: Change vendor string to "Intel Open Source Technology Center".Kenneth Graunke2012-06-011-1/+1
| | | | | | | | | | | | | | | | | | | Tungsten Graphics has not existed for several years, and the majority of ongoing development and support is done by Intel. I chose to include "Open Source Technology Center" to distinguish it from, say, the closed source Windows OpenGL driver. The one downside to this patch is that applications that pattern match against "Intel" may start applying workarounds meant for the Windows driver. However, it does seem like the right thing to do. This does change oglconform behavior. Acked-by: Eric Anholt <[email protected]> Acked-by: Ian Romanick <[email protected]> Acked-by: Eugeni Dodonov <[email protected]> Acked-by: Keith Packard <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]>
* scons: add code to generate the various GL API filesBrian Paul2012-05-311-0/+2
| | | | | | | This fixes recent build breakage when we began building the generated API files from xml as part of the normal build process. Fixes http://bugs.freedesktop.org/show_bug.cgi?id=50475
* mesa: don't compile integer clear shaders for unsupported APIsOliver McFadden2012-05-301-1/+1
| | | | | | | | | | | | | | Discovered while running the Khronos conformance test suite and receiving "implementation error: meta program compile failed." This bug was recently introduced by the i965 clear patch set and would only be detected while using the ES2 API and only on gen6+ hardware. Signed-off-by: Oliver McFadden <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/blorp: Implement destination clipping and scissoringPaul Berry2012-05-291-5/+67
| | | | | This patch implements clipping and scissoring of the destination rect for blits that use the blorp engine (e.g. MSAA blits).
* i830: Fix crash for GL_STENCIL_TEST in i830Enable()Kurt Roeckx2012-05-291-1/+1
| | | | | | | | | | | commit 87f12bb2d95236c7b025d1a8be56b5ab1683d702 tried to fix rb->mt being NULL, but change this case wrong. NOTE: This is a candidate for the 8.0 branch. Signed-off-by: Kurt Roeckx <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/msaa: Enable 4x MSAA on Gen7.Paul Berry2012-05-252-9/+9
| | | | | | | | | | | | | | | | | | Basic 4x MSAA support now works on Gen7. This patch enables it. As with Gen6, MSAA support is still fairly preliminary. In particular, the following are not yet supported: - 8x oversampling (Gen7 has hardware support for this, but we do not yet expose it). - Fully general blits between MSAA and non-MSAA buffers. - Formats other than RGBA8, DEPTH24, and STENCIL8. - Centrold interpolation. - Coverage parameters (glSampleCoverage, GL_SAMPLE_ALPHA_TO_COVERAGE, GL_SAMPLE_ALPHA_TO_ONE, GL_SAMPLE_COVERAGE, GL_SAMPLE_COVERAGE_VALUE, GL_SAMPLE_COVERAGE_INVERT). Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/msaa: Implement manual blending operation for Gen7.Paul Berry2012-05-251-23/+67
| | | | | | | | | | | | | | | On Gen6, the blending necessary to blit an MSAA surface to a non-MSAA surface could be accomplished with a single texturing operation. On Gen7, the WM program must fetch each sample and blend them together manually. From the Bspec (Shared Functions/Messages/Initiating Message/Message Types/sample): [DevIVB+]:Number of Multisamples on the associated surface must be MULTISAMPLECOUNT_1. This patch implements the manual blend operation. Acked-by: Kenneth Graunke <[email protected]>
* i965/msaa: Modify blorp code to account for Gen7 MSAA layouts.Paul Berry2012-05-253-68/+151
| | | | | | | | | | | | | | | | | | | Since blorp uses color textures and render targets to do all its work (even when blitting stencil and depth data), it always has to configure the Gen7 GPU to use the new "sliced" MSAA layout. However, when blitting stencil or depth data, the actual MSAA layout is interleaved (as in Gen6). Therefore, blorp has to do extra coordinate transformation work to account for the interleaving manually. This patch causes blorp to perform the necessary extra coordinate transformations. It also modifies the blorp SURFACE_STATE setup code for Gen7, so that it does not try to correct the surface width and height to account for MSAA, since "sliced" MSAA layout doesn't affect the surface width or height. Acked-by: Kenneth Graunke <[email protected]>
* i965/msaa: Validate Gen7 surface state constraints.Paul Berry2012-05-253-3/+109
| | | | | | | | | When a Gen7 SURFACE_STATE is configured for MSAA, a number of additional constaints come in to play. This patch adds a function gen7_check_surface_setup() which verifies that all of those constraints are met. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/msaa: Properly handle sliced layout for Gen7.Paul Berry2012-05-2510-58/+162
| | | | | | | | | | | | | | | | | | | | | | | | | Starting in Gen7, there are two possible layouts for MSAA surfaces: - Interleaved, in which additional samples are accommodated by scaling up the width and height of the surface. This is the only layout available in Gen6. On Gen7 it is used for depth and stencil surfaces only. - Sliced, in which the surface is stored as a 2D array, with array slice n containing all pixel data for sample n. On Gen7 this layout is used for color surfaces. The "Sliced" layout has an additional requirement: it must be used in ARYSPC_LOD0 mode, which means that the surface doesn't leave any extra room between array slices for miplevels other than 0. This patch modifies the surface allocation functions to use the correct layout when allocating MSAA surfaces in Gen7, and to set the array offsets properly when using ARYSPC_LOD0 mode. It also modifies the code that populates SURFACE_STATE structures to ensure that ARYSPC_LOD0 mode is selected in the appropriate circumstances. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/msaa: Add defines for Gen7.Paul Berry2012-05-251-0/+5
| | | | | | Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/blorp: Enable blorp blits on Gen7.Paul Berry2012-05-252-2/+4
| | | | | | | | | | | | | Gen7 support for blorp (blits using the render bath) now works for non-MSAA purposes. This patch enables it. Since blorp operations re-use the logic for HiZ ops, this required adding a case to the switch statement in gen7_blorp_emit_wm_config(), to allow for the case where no HiZ op is being performed. Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/blorp: Implement proper texel fetch messages for Gen7.Paul Berry2012-05-252-2/+31
| | | | | | | | | | | | | | | | | On Gen6, texel fetch is always accomplished using the SAMPLE_LD message, which accepts arguments (u, v, r, lod, si). On Gen7, there are two* texel fetch messages: SAMPLE_LD for non-MSAA surfaces, taking arguments (u, lod, v), and SAMPLE_LD2DSS for MSAA surfaces, taking arguments (si, u, v). *Technically, there are other texel fetch messages, but they are used for "compressed" MSAA surfaces, which we don't yet support. This patch adds the proper message types and argument orderings for Gen7. Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/blorp: Use 16 pixel dispatch on Gen7.Paul Berry2012-05-251-1/+9
| | | | | | | | | | | | | | | | | Gen7 hardware requires us to enable at least one WM dispatch mode, even if there is no program being dispatched to. When this code was only used for HiZ operations (which don't use a WM program), we used 32-pixel dispatch, because it didn't matter. But blit programs are compiled for 16-pixel dispatch. So just enable 16-wide dispatch unconditionally. Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> v2: Enable 16-wide dispatch unconditionally rather than add the unnecessary complication of using 32-wide dispatch when there is no WM program.
* i965/blorp: Allocate space for push constants on Gen7.Paul Berry2012-05-253-30/+28
| | | | | | | | | | | | | | | | | | On Gen7, push constants for shader programs are stored in the URB, so blorp code needs to set aside space for them. This was previously unnecessary because blorp code was based on HiZ operations, which don't require any shaders. This patch adds a call from gen7_blorp_exec() to gen7_allocate_push_constants(), to ensure that push constants are assigned the correct location in the URB. It also extracts a new function gen7_emit_urb_state() from gen7_upload_urb(), which is re-used by gen7_blorp_emit_urb_config() to ensure that the URB regions used by all the pipeline stages leave room for the push constants. Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-19 17:04:49 +0000