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* r600: don't force Z orderAlex Deucher2009-11-161-3/+0
| | | | | | | Let the hw decide (early vs late Z) fixes fdo bug 25092 Signed-off-by: Alex Deucher <[email protected]>
* mesa: remove unused vertex array driver hooksBrian Paul2009-11-161-13/+0
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* i965: Share OPCODE_TXB between brw_wm_emit.c and brw_wm_glsl.cEric Anholt2009-11-133-101/+63
| | | | This should fix TXB on G45 and older in the GLSL case.
* i965: Share OPCODE_TEX between brw_wm_emit.c and brw_wm_glsl.c.Eric Anholt2009-11-133-118/+72
| | | | | New comments should explain some of the confusion about how this message works.
* i965: Clean up emit_tex a bit.Eric Anholt2009-11-131-27/+24
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* Merge remote branch 'origin/mesa_7_6_branch'Eric Anholt2009-11-1310-46/+81
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| * i965: Fix Ironlake shadow comparisons.Eric Anholt2009-11-121-7/+17
| | | | | | | | The cube map array index arg is always present.
| * i965: Fix VBO last-valid-offset setup on Ironlake.Eric Anholt2009-11-121-10/+3
| | | | | | | | | | Instead of doing math based on the (broken for VBO && offset != 0) input->count number, just use the BO size. Fixes assertion failure in ETQW.
| * i965: fix EXT_provoking_vertex supportRoland Scheidegger2009-11-118-29/+61
| | | | | | | | | | | | | | | | This didn't work for quad/quadstrips at all, and for all other primitive types it only worked when they were unclipped. Fix up the former in gs stage (could probably do without these changes and instead set QuadsFollowProvokingVertexConvention to false), and the rest in clip stage.
* | i965: Flag BRW_NEW_CONTEXT on some context state.Eric Anholt2009-11-132-6/+6
| | | | | | | | | | | | Fixing this is a prereq for avoiding flagging all state at new batch time. Eliminating that still causes problems, though (notably glean logicOp fails on my GM965).
* | intel: Remove some dead context structure fields.Eric Anholt2009-11-131-2/+0
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* | i965: Remove an unused cache_item field.Eric Anholt2009-11-133-3/+1
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* | i965: Remove long dead structures for ffvertex_prog.c.Eric Anholt2009-11-131-17/+0
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* | i965: Use bo_map instead of subdata to upload the bits of constant buffer.Eric Anholt2009-11-132-2/+26
| | | | | | | | Saves CPU time, resulting in a 2.5% FPS win on ETQW.
* | i965: Validate the number of URB entries selected for the VS.Eric Anholt2009-11-131-4/+33
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* | intel: When subdataing a busy buffer, use a temporary and blit in.Eric Anholt2009-11-131-3/+16
| | | | | | | | | | | | This cuts a massive number of waits in ET:QW, which uses a VBO ringbuffer. Unfortunately it doesn't BufferData when wrapping back to 0, so we can't be clever with tracking what's been initialized.
* | i965: Clean up Ironlake sampler type definitions.Eric Anholt2009-11-133-18/+10
| | | | | | | | They're the same regardless of execution width for 8, 4x2, and 16.
* | i965: Avoid moving the current value back into the accumulator for MAD.Eric Anholt2009-11-131-1/+34
| | | | | | | | | | This is a 2.9% (+/-.3%) performance win for my GL demo, which hits MAD sequences for matrix transforms.
* | intel: Don't check for context pointer to be NULL during extension initIan Romanick2009-11-121-7/+6
| | | | | | | | | | | | | | | | | | | | Thanks to Chia-I Wu's changes to the extension function infrastructure, we no longer have to tell the loader which extensions the driver might enable. This means that intelInitExtensions will never be called with a NULL context pointer. Remove all the NULL checks. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* | intel: Remove unused enable_imaging parameter to intelInitExtensionsIan Romanick2009-11-123-6/+4
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* | r300, r300g: Add missing registers.Corbin Simpson2009-11-111-0/+2
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* | Merge remote branch 'origin/mesa_7_6_branch'Eric Anholt2009-11-101-1/+11
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| * i965: Fix VS constant buffer value loading.Eric Anholt2009-11-101-1/+11
| | | | | | | | | | | | | | | | | | | | Previously, we'd load linearly from ParameterValues[0] for the constants, though ParameterValues[1] may not equal ParameterValues[0] + 4. Additionally, the STATE_VAL type paramters didn't get updated. Fixes piglit vp-constant-array-huge.vpfp and ET:QW object locations. Bug #23226.
| * i965: Unalias src/dst registers for SGE and friends.Eric Anholt2009-11-101-19/+21
| | | | | | | | | | | | | | Fixes piglit vp-sge-alias test, and the googleearth ground shader. \o/ Bug #22228 (cherry picked from commit 56ab92bad8f1d05bc22b8a8471d5aeb663f220de)
| * i965: Allow use of PROGRAM_LOCAL constants in ARB_vp.Eric Anholt2009-11-101-1/+1
| | | | | | | | | | Fixes piglit arl.vp. (cherry picked from commit d52d78b4bcd6d4c0578f972c0b8ebac09e632196)
| * r600: don't emit htile regsAlex Deucher2009-11-091-4/+2
| | | | | | | | | | | | These are needed for HiZ which is not currently used and the _BASE reg requires a reloc which is not currently supported in the drm.
* | i965: avoid memsetting all the BRW_WM_MAX_INSN arrays for every compile.Eric Anholt2009-11-104-4/+23
| | | | | | | | | | | | | | | | | | For an app that's blowing out the state cache, like sauerbraten, the memset of the giant arrays ended up taking 11% of the CPU even when only a "few" of the entries got used. With this, the WM program compile drops back down to 1% of CPU time. Bug #24981 (bisected to BRW_WM_MAX_INSN increase).
* | i965: Add a note explaining the data cache domain.Eric Anholt2009-11-101-1/+4
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* | i965: Unalias src/dst registers for SGE and friends.Eric Anholt2009-11-101-19/+21
| | | | | | | | | | | | Fixes piglit vp-sge-alias test, and the googleearth ground shader. \o/ Bug #22228
* | i965: Allow use of PROGRAM_LOCAL constants in ARB_vp.Eric Anholt2009-11-101-1/+1
| | | | | | | | Fixes piglit arl.vp.
* | r600/r700: typo, fix mask of DB_ALPHA_TO_MASKJerome Glisse2009-11-091-3/+3
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* | r600: rework DB render setupAlex Deucher2009-11-094-42/+73
| | | | | | | | | | | | | | - consolidate DB render setup - only enable perfect ZPASS counts and cull disable when OQ is active - enable early Z
* | r600: don't emit htile regsAlex Deucher2009-11-091-4/+2
| | | | | | | | | | | | These are needed for HiZ which is not currently used and the _BASE reg requires a reloc which is not currently supported in the drm.
* | r600: add missing ZPASS setup bits for r7xx+Alex Deucher2009-11-092-0/+6
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* | i965: Use Compr4 instruction compression mode on G4X and newer.Eric Anholt2009-11-063-17/+29
| | | | | | | | | | | | | | No statistically significant performance difference at n=3 with either openarena or my GL demo, but cutting program size seems like a good thing to be doing for the hypothetical app that has a working set near icache size.
* | i965: Share min/max between brw_wm_emit.c and brw_wm_glsl.cEric Anholt2009-11-063-60/+72
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* | i965: Share emit_fb_write() between brw_wm_emit.c and brw_wm_glsl.cEric Anholt2009-11-064-127/+40
| | | | | | | | This should fix issues with antialiased lines in GLSL.
* | i965: Share most of the WM functions between brw_wm_glsl.c and brw_wm_emit.cEric Anholt2009-11-063-297/+109
| | | | | | | | | | The PINTERP code should be faster for brw_wm_glsl.c now since brw_wm_emit.c's had been improved, and pixel_w should no longer stomp on a neighbor to dst.
* | i965: Share math functions between brw_wm_glsl.c and brw_wm_emit.c.Eric Anholt2009-11-063-221/+111
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* | i965: Share the sop opcodes between brw_wm_glsl.c and brw_wm_emit.c.Eric Anholt2009-11-063-74/+29
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* | i965: Share OPCODE_MAD between brw_wm_glsl.c and brw_wm_emit.cEric Anholt2009-11-063-30/+13
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* | i965: Share the DP3, DP4, and DPH between brw_wm_glsl.c and brw_wm_emit.cEric Anholt2009-11-063-99/+33
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* | i965: Add generic GLSL code for unaliasing a 3-arg opcode, and share LRP code.Eric Anholt2009-11-063-45/+71
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* | i965: Use a normal alu1 emit for OPCODE_TRUNC.Eric Anholt2009-11-062-34/+2
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* | i965: Share basic ALU ops between brw_wm_glsl and brw_wm_emit.cEric Anholt2009-11-063-117/+38
| | | | | | | | | | This drops support for get_src_reg_imm in these, but the prospect of getting brw_wm_pass*.c onto our GLSL path is well worth some temporary pain.
* | i965: Collect GLSL src/dst regs up in generic code.Eric Anholt2009-11-062-7/+17
| | | | | | | | | | | | | | | | This matches brw_wm_emit.c, which we'll be using shortly. There's a possible penalty here in that we'll allocate registers for unused channels, since we aren't doing ref tracking like brw_wm_pass*.c does. However, my measurements on GM965 don't show any for either OA or UT2004 with the GLSL path forced.
* | intel: better front color buffer test in intelClear()Brian Paul2009-11-061-2/+3
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* | i965: Always pass the size argument to brw_cache_data.Eric Anholt2009-11-066-57/+21
| | | | | | | | | | This keeps the individual state files from having to export their structures for brw_state_cache initialization.
* | intel: Finish removing the fallback code for bug #16697.Eric Anholt2009-11-061-6/+2
| | | | | | | | I fixed it properly as of 7216679c1998b49ff5b08e6b43f8d5779415bf54.
* | intel: Don't validate in a texture image used as a render target.Eric Anholt2009-11-063-11/+15
| | | | | | | | | | Otherwise, we could lose track of rendering to that image, which could easily happen during mipmap generation.
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