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* i965/fs: Complete TXL support on gen5+.Kenneth Graunke2011-02-251-0/+7
* i965/fs: Complete TXL support on gen4.Kenneth Graunke2011-02-251-0/+10
* i965/fs: Use a properly named constant in TXB handling.Kenneth Graunke2011-02-251-1/+1
* i965: Add #defines for gen4 SIMD8 TXB/TXL with shadow comparison.Kenneth Graunke2011-02-251-0/+2
* i965: Increase Sandybridge point size clamp in the clip state.Kenneth Graunke2011-02-241-1/+1
* intel: Try using glCopyTexSubImage2D in _mesa_meta_BlitFramebufferNeil Roberts2011-02-243-22/+108
* i965: Remember to pack the constant blend color as floats into the batchChris Wilson2011-02-241-4/+4
* intel: Reset the buffer offset after releasing reference to packed uploadChris Wilson2011-02-242-58/+77
* i965: Unmap the correct pointer after discontiguous uploadChris Wilson2011-02-241-2/+3
* intel: Protect against waiting on a NULL render target boChris Wilson2011-02-241-1/+1
* intel: gen3 is particular sensitive to batch sizeChris Wilson2011-02-231-1/+1
* i915: And remember assign the new value to the state reg...Chris Wilson2011-02-231-0/+1
* xlib: pass Display pointer to XMesaGarbageCollect()Andy Skinner2011-02-223-7/+7
* i965: Increase Sandybridge point size clamp.Kenneth Graunke2011-02-221-1/+1
* i965/fs: Correctly set up gl_FragCoord.w on Sandybridge.Kenneth Graunke2011-02-221-1/+1
* i965/fs: Refactor control flow stack handling.Kenneth Graunke2011-02-221-7/+27
* i965/fs: Avoid register coalescing away gen6 MATH workarounds.Kenneth Graunke2011-02-221-0/+10
* i965/fs: Apply source modifier workarounds to POW as well.Kenneth Graunke2011-02-221-3/+7
* i965: Fix shaders that write to gl_PointSize on Sandybridge.Kenneth Graunke2011-02-221-0/+2
* i965: Trim the interleaved upload to the minimum number of verticesChris Wilson2011-02-221-1/+5
* i965: Reinstate max-index paranoiaChris Wilson2011-02-221-1/+1
* i965: Zero the offset into the vbo when uploading non-interleavedChris Wilson2011-02-221-0/+1
* i965: Fix VB packet reuse when offset for the new buffer isn't stride aligned.Eric Anholt2011-02-211-1/+1
* radeon: add default switch case to silence unhandled enum warningBrian Paul2011-02-211-0/+2
* intel: Fix insufficient integer width for upload buffer offsetChris Wilson2011-02-211-2/+2
* i965: Remove spurious duplicate ADVANCE_BATCHChris Wilson2011-02-211-1/+0
* i915: Emit a single relocation per vboChris Wilson2011-02-215-17/+45
* i915: Suppress emission of redundant stencil updatesChris Wilson2011-02-211-45/+55
* i915: Separate BLEND from general context state.Chris Wilson2011-02-213-22/+40
* i915: Only flag context changes if the actual state is changedChris Wilson2011-02-211-49/+105
* i915: suppress repeated sampler state emissionChris Wilson2011-02-212-0/+11
* i915: Eliminate redundant CONSTANTS updatesChris Wilson2011-02-211-25/+26
* i965: Use compiler builtins when availableChris Wilson2011-02-212-11/+8
* i965: Micro-optimise check_stateChris Wilson2011-02-211-7/+5
* intel: use throttle ioctl for throttlingChris Wilson2011-02-213-13/+3
* i965: Remove unused 'next_free_page' memberChris Wilson2011-02-211-5/+0
* intel: Skip the flush before read-pixels via blitChris Wilson2011-02-211-4/+7
* intel: extend current vertex buffersChris Wilson2011-02-215-23/+73
* intel: Use specified alignment for writes into the upload bufferChris Wilson2011-02-213-30/+57
* i965: Clean up brw_prepare_vertices()Chris Wilson2011-02-211-21/+20
* intel: combine short memcpy using a temporary allocated bufferChris Wilson2011-02-213-38/+27
* i965: upload normal arrays as interleavedChris Wilson2011-02-211-30/+72
* i965: interleaved vboChris Wilson2011-02-211-12/+27
* i965: emit one vb packet per vboChris Wilson2011-02-213-77/+83
* i965: upload transient indices into the same discontiguous bufferChris Wilson2011-02-212-13/+8
* i965: suppress repeat-emission of identical vertex elementsChris Wilson2011-02-211-3/+2
* i965: Move repeat-instruction-suppression to batchbuffer coreChris Wilson2011-02-219-152/+120
* intel: use pwrite for batchChris Wilson2011-02-2127-302/+219
* i965: drop state_bo references to batch_boChris Wilson2011-02-219-105/+74
* i965: directly write wm state to batchChris Wilson2011-02-211-63/+48
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