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* radeon: Always initialize front and back renderbuffers if presentNicolai Hähnle2009-06-271-2/+1
| | | | | | This fixes an assertion in glReadPixels from the front buffer. Signed-off-by: Nicolai Hähnle <[email protected]>
* radeon: Update .gitignoreNicolai Hähnle2009-06-272-2/+25
| | | | | | | Add all source files that are symlink'ed from common radeon code to the ignore list. Signed-off-by: Nicolai Hähnle <[email protected]>
* Merge branch 'arb_vertex_array_object'Brian Paul2009-06-262-19/+47
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| * intel: enable GL_ARB_vertex_array_object extensionBrian Paul2009-06-221-0/+2
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| * mesa: regenerated files related to GL_ARB_vertex_array_objectBrian Paul2009-06-191-19/+45
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* | Merge branch 'mesa_7_5_branch'Brian Paul2009-06-261-0/+11
|\ \ | | | | | | | | | | | | | | | | | | | | | Conflicts: Makefile src/gallium/drivers/softpipe/sp_screen.c src/mesa/main/version.h
| * | intel / DRI2: Additional flush of fake front-buffer to real front-bufferIan Romanick2009-06-261-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To maintain correctness, the server will copy the real front-buffer to a newly allocated fake front-buffer in DRI2GetBuffersWithFormat. However, if the DRI2GetBuffersWithFormat is triggered by glViewport, this will copy stale data into the new buffer. Fix this by flushing the current fake front-buffer to the real front-buffer in intel_viewport. Fixes bug #22288.
* | | i965: fix fetching constants from constant buffer in glsl pathRoland Scheidegger2009-06-264-17/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | the driver used to overwrite grf0 then use implicit move by send instruction to move contents of grf0 to mrf1. However, we must not overwrite grf0 since it's still used later for fb write. Instead, do the move directly do mrf1 (we could use implicit move from another grf reg to mrf1 but since we need a mov to encode the data anyway it doesn't seem to make sense). I think the dp_READ/WRITE_16 functions may suffer from the same issue. While here also remove unnecessary msg_reg_nr parameter from the dataport functions since always message register 1 is used.
* | | r200: make use of DMA buffers for Elts a lot better.Dave Airlie2009-06-263-16/+19
| | | | | | | | | | | | | | | This allows us to return the unused portion of the dma buffer to the allocator instead of wasting nearly 16k a pop.
* | | r200: only emit unitneeded texturesDave Airlie2009-06-261-0/+2
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* | | radeon: fix hw texture limitsRoland Scheidegger2009-06-253-9/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | still always enable max, but the right values this time. More work should probably be done for saner limits without mm, and/or dri conf option allow_large_textures (which is ignored) removed. 3D limit on r100 is pretty arbitrary as still handled by swrast anyway. Also fix r300 limits (except 3d I've no idea what the max is anyway so keep using mesa default).
* | | radeon/r200: add some hw texture limitsDave Airlie2009-06-252-2/+8
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* | | radeon: fix stupidity in cs space check code.Dave Airlie2009-06-251-2/+6
| | | | | | | | | | | | This was already correct in the GEM code
* | | intel: fix additional merge conflicts missed in previous commitBrian Paul2009-06-242-18/+0
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* | | Merge branch 'mesa_7_5_branch'Brian Paul2009-06-244-1/+22
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: src/mesa/drivers/dri/i915/i915_tex_layout.c src/mesa/drivers/dri/i965/brw_wm_glsl.c src/mesa/drivers/dri/intel/intel_buffer_objects.c src/mesa/drivers/dri/intel/intel_pixel_bitmap.c src/mesa/drivers/dri/intel/intel_pixel_draw.c src/mesa/main/enums.c src/mesa/main/texstate.c src/mesa/vbo/vbo_exec_array.c
| * | i965: handle OPCODE_SWZ in the glsl pathRoland Scheidegger2009-06-221-0/+1
| | | | | | | | | | | | | | | | | | | | | glsl compiler will not generate OPCODE_SWZ, and as a first step it would be translated away to a MOV anyway (why?), but later internally this opcode is generated (for EXT_texture_swizzling). (cherry picked from commit 4ef1f8e3b52a06fcf58f78c9c36738531b91dbac)
| * | intel: intel_texture_drawpixels() can't handle GL_DEPTH_STENCIL.Michel Dänzer2009-06-221-1/+1
| | | | | | | | | | | | | | | Fixes glean depthStencil test. (cherry picked from commit 3885b708fdbb7bbd5dd3a247c41fb9a75ee7c057)
| * | i965: added intelFlush() call in intel_get_tex_image()Brian Paul2009-06-221-0/+6
| | | | | | | | | | | | | | | Fixes the render-to-texture test in progs/tests/getteximage.c (cherry picked from commit a03b349153660e449daf4f56d750f1caef23b1a5)
| * | intel: Fix other metaops versus GL_COMPILE_AND_EXECUTE dlists.Eric Anholt2009-06-192-3/+3
| | | | | | | | | | | | | | | | | | Fixes oglconform zbfunc.c and pxtrans-cidraw.c, at least. (cherry picked from commit 405300bb190f516e16b704050abe3389b366ed27)
| * | intel: Fix glClear behavior versus display lists.Eric Anholt2009-06-191-1/+1
| | | | | | | | | | | | | | | | | | | | | The CALL_DrawArrays was leaking the clear's primitives into the display list with GL_COMPILE_AND_EXECUTE. Use _mesa_DrawArrays instead, which doesn't appear to leak. Fixes piglit dlist-clear test. (cherry picked from commit 64edde1004f7a69e77877bba24d315a92bcd47c8)
| * | radeons: use dp4 for position invariant vertex programsRoland Scheidegger2009-06-193-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | Fixes #22181. R200 requires this since DP4 is used in hw tnl mode. R300 prefers it (should be faster due to no instruction dependencies), but both methods should be correct (when sw tcl is used though, MUL/MAD might be faster). Probably doesn't make much difference for R100 since vertex progs are executed in software anyway, but let's just keep it the same there too.
| * | intel: remove extra \n from warning stringBrian Paul2009-06-171-1/+1
| | | | | | | | | | | | (cherry picked from commit 42e9bde0fa2276b8f5bb434328eea7665794b127)
| * | i965: fix 1D texture borders with GL_CLAMP_TO_BORDERRobert Ellison2009-06-171-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With 1D textures, GL_TEXTURE_WRAP_T should be ignored (only GL_TEXTURE_WRAP_S should be respected). But the i965 hardware seems to follow the value of GL_TEXTURE_WRAP_T even when sampling 1D textures. This fix forces GL_TEXTURE_WRAP_T to be GL_REPEAT whenever 1D textures are used; this allows the texture to be sampled correctly, avoiding "imaginary" border elements in the T direction. This bug was demonstrated in the Piglit tex1d-2dborder test. With this fix, that test passes. (cherry picked from commit ab6c4fa582972e25f8800c77b5dd5b3a83afc996)
| * | i965: send all warnings through _mesa_warning()Robert Ellison2009-06-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | One warning message: drm_i915_getparam: -22 was still being sent to fprintf(). This causes all Piglit tests to fail, even with MESA_DEBUG=0. Using _mesa_warning() to emit the message allows the general Mesa controls for messages like this to be applied. (cherry picked from commit bc3270e99f5c39544aaf831742db14796ab83a6a)
| * | i965: fix segfault on low memory conditionsRobert Ellison2009-06-171-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | When out of memory (in at least one case, triggered by a longrunning memory leak), this code will segfault and crash. By checking for the out-of-memory condition, the system can continue, and will report the out-of-memory error later, a much preferable outcome. (cherry picked from commit 44a4abfd4f8695809eaec07df8eeb191d6e017d7)
| * | i915: Don't put VBOs in graphics memory unless required for an operation.Eric Anholt2009-06-172-1/+40
| | | | | | | | | | | | | | | | | | This saves doing swtnl from uncached memory, which is painful. Improves clutter test-text performance by 10% since it started using VBOs. (cherry picked from commit a945e203d4fe254593bc0c5c5d6caca45e65f9f7)
| * | i915: Fall back on NPOT textured metaops on 830-class.Eric Anholt2009-06-173-0/+30
| | | | | | | | | | | | (cherry picked from commit 8ec6e036792decf5149a209e51cb5e93ccc5c754)
| * | i915: Restore the Viewport and DepthRange functions on 8xx.Eric Anholt2009-06-171-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | Fixes failed viewport updates on glxgears (and other apps) resize since e41780fedc2c1f22b43118da30a0103fa68b769f. Bug #20473. (cherry picked from commit 0e83e8f51af07a3066519f169f07d9afbf23252e)
| * | i956: Make state dependency of SF on drawbuffer bounds match Mesa's.Eric Anholt2009-06-171-2/+5
| | | | | | | | | | | | | | | | | | | | | Noticed while debugging a weird 1D FBO testcase that left its existing viewport and projection matrix in place when switching drawbuffers. Didn't fix the testcase, though. (cherry picked from commit 3a521d84ecc646fcc65fa3fe7c5f1fdbdebe8bc2)
| * | intel: Don't complain on falling back from PBO fastpaths.Eric Anholt2009-06-171-3/+3
| | | | | | | | | | | | | | | | | | | | | Instead, stash the debug info under the handy debug flag. Bug #20053 (cherry picked from commit 22690482e692cb5ed2f84d3e69545c09292e3484)
| * | i915: Use Stencil.Enabled instead of Stencil._Enabled in DrawBuffers.Eric Anholt2009-06-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The _Enabled field isn't updated at the point that DrawBuffers is called, and the Driver.Enable() function does the testing for stencil buffer presence anyway. bug #21608 for Radeon (cherry picked from commit 4c6f82989983eecc0b3b724716cb3bcb675664c5)
| * | i915: Only use the new 945 cube layout for compressed textures.Eric Anholt2009-06-171-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The docs actually explain this, but not in a terribly clear manner. This nearly fixes the piglit cubemap testcase, except that something's going wrong with the nearest filtering at 2x2 sizes in the testcase. Looks good by visual inspection, though. Bug #21692 (cherry picked from commit 5c5a46884899ea25cdf25545d6ab3d9a74eafa3a)
| * | i965: Fix varying payload reg assignment for the non-GLSL-instructions path.Eric Anholt2009-06-171-8/+10
| | | | | | | | | | | | | | | I don't have a testcase for this, but it seems clearly wrong. (cherry picked from commit dc657f3929fbe03275b3fae4ef84f02e74b51114)
| * | i965: Fix register allocation of GLSL fp inputs.Eric Anholt2009-06-174-13/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before, if the VP output something that is in the attributes coming into the WM but which isn't used by the WM, then WM would end up reading subsequent varyings from the wrong places. This was visible with a GLSL demo using gl_PointSize in the VS and a varying in the WM, as point size is in the VUE but not used by the WM. There is now a regression test in piglit, glsl-unused-varying. (cherry picked from commit 0f5113deed91611ecdda6596542530b1849bb161)
| * | intel: Use FRONT_AND_BACK for StencilOp as well.Eric Anholt2009-06-171-1/+2
| | | | | | | | | | | | (cherry picked from commit 64980125c76b05501a6fe7fe20fe52438f459129)
| * | intel: Use GL_FRONT_AND_BACK for stencil clearing.Eric Anholt2009-06-171-1/+2
| | | | | | | | | | | | | | | | | | This comes from a radeon-rewrite fallback fix, but may also fix stencil clear failure when the polygon winding mode is flipped. (cherry picked from commit d866abeffc7e4a29736fa35fb8ac09c3a28a44d6)
| * | intel: Skip the DRI2 renderbuffer update when doing Viewport on an FBO.Eric Anholt2009-06-171-1/+1
| | | | | | | | | | | | (cherry picked from commit d4a42b0ce6455d03be70aa56aacd779be193aca4)
| * | intel: Map write-only buffer objects through the GTT when possible.Eric Anholt2009-06-172-2/+15
| | | | | | | | | | | | | | | | | | This looks to be a win of a few percent in cairogears with new vbo code, thanks to not polluting caches. (cherry picked from commit aa422b262509bc0763a50f63a51a1730139ea52f)
| * | mesa: added null ptr check in Fake_glXCreatePixmap()Brian Paul2009-06-171-1/+1
| | | | | | | | | | | | Fixes segfault in progs/xdemos/glxgears_pixmap.c
| * | GLX: attempt to fix glean makeCurrent test cases.Brian Paul2009-06-171-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Two parts to this: One we don't keep pointers to possibly freed memory anymore once we unbind the drawables from the context. Brian I need to figure out what the comment you made there, can we get a glean/piglit test so we can fix it properly? If the new gc is the same as the oldGC, we call the unbind even though we just bound it in that function. doh. (cherry picked from master, commit 77506dac8e81e9548a7e9680ce367175fe5747af)
* | | i965: Disable texture tiling by default.Eric Anholt2009-06-231-5/+1
| | | | | | | | | | | | | | | I haven't fixed all the regressions yet, and it'll be easy to re-enable when the known problems are fixed.
* | | i965: Set the max index buffer address correctly according to the docs.Eric Anholt2009-06-231-1/+1
| | | | | | | | | | | | It's the last addressable byte, not the byte after the end of the buffer.
* | | i965: Don't set a reserved bit in MI_FLUSH.Eric Anholt2009-06-231-1/+1
| | | | | | | | | | | | | | | I noticed this when this MI_FLUSH showed up in IPEHR for the ut2004 hang. Not setting the reserved bit didn't help, though.
* | | i965: Fix depth-texture Y-tiling detection for sized internal formats.Eric Anholt2009-06-234-3/+9
| | | | | | | | | | | | Fixes assertion failure on norsetto shadow mapping demo.
* | | i965: Fix packed depth/stencil textures to be Y-tiled as well.Eric Anholt2009-06-232-1/+4
| | | | | | | | | | | | Fixes shadowtex.c. And an assert is added to catch this sooner next time.
* | | intel: Bail on blits with non-tile-aligned offsets.Eric Anholt2009-06-231-6/+18
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* | | intel: Avoid trying to do blits to Y tiled regions.Eric Anholt2009-06-2310-90/+137
| | | | | | | | | | | | | | | | | | | | | | | | This is somewhat nasty, but we need to do Y-tiled depth for FBO support. May help with corruption and hangs since enabling texture tiling, and since switching depth textures to Y tiled. Fixes piglit depthtex.c on 965.
* | | intel: Fix some potential writes to zero-copy PBOs when used as regions.Eric Anholt2009-06-235-10/+13
| | | | | | | | | | | | | | | | | | I was in the midst of fixing some blitting-with-Y-tiled issues when I noticed this. Hopefully PBO usage will be a little more robust, as a result.
* | | intel: Remove long-unused intel_region_fill and intelEmitFillBlit.Eric Anholt2009-06-234-106/+0
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* | | intel: Refuse to do texture tiling if we don't have the kernel support.Eric Anholt2009-06-231-0/+6
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