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* i965: Allow disk shader cache usage with LINKING_SUCCESS statusJordan Justen2018-03-191-3/+0
| | | | | | | | | | | | | | | | | | | | Currently, we only look in the disk shader cache if we see that the shader program is in the cache during the link step. If the shader cache entry isn't found during the program link, there are still some (fairly unlikely) scenarios where later it might be useful to search the cache for gen binary programs. 1. If the cache evicts the serialized glsl cache, there might still be valid gen program entries in the disk cache. 2. If two applications are running in parallel, then it is possible that one may write out the cached gen program item which the other application can then make use of. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* i965: Allow disk shader cache usage with transform feedbackJordan Justen2018-03-191-8/+0
| | | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105444 Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* i965: Add INTEL_DEBUG stages support for disk shader cacheJordan Justen2018-03-191-0/+26
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: silence unused function warningLionel Landwerlin2018-03-151-1/+1
| | | | | | | | | | [123/227] Compiling C object 'src/mesa/drivers/dri/i965/libi965_gen110@sta/genX_blorp_exec.c.o'. ../src/mesa/drivers/dri/i965/genX_blorp_exec.c:99:1: warning: ‘blorp_get_surface_base_address’ defined but not used [-Wunused-function] blorp_get_surface_base_address(struct blorp_batch *batch) ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* i965: Emit texture cache invalidates around blorp_copyJason Ekstrand2018-03-131-0/+15
| | | | | | | | | | | This is a terrible hack but it fixes CTS regressions. It's still incredibly unclear exactly what is going wrong in the hardware to cause this to be an issue so this isn't a good fix by any means. However, it does fix tests so there is that. Fixes: fb0e9b5197 "i965: Track the depth and render caches separately" Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103746 Acked-by: Kenneth Graunke <[email protected]>
* x11: remove empty GLX_SGIX_swap_group stubsEmil Velikov2018-03-123-34/+0
| | | | | | | | | | | The extension was never implemented. Quick search suggests: - no actual users (on my Arch setup) - the Nvidia driver does not implement the extension Signed-off-by: Emil Velikov <[email protected]> Acked-by: Ian Romanick <[email protected]> Acked-by: Brian Paul <[email protected]> Reviewed-by: Adam Jackson <[email protected]>
* x11: remove empty GLX_SGIX_swap_barrier stubsEmil Velikov2018-03-123-57/+0
| | | | | | | | | | | The extension was never implemented. Quick search suggests: - no actual users (on my Arch setup) - the Nvidia driver does not implement the extension Signed-off-by: Emil Velikov <[email protected]> Acked-by: Ian Romanick <[email protected]> Acked-by: Brian Paul <[email protected]> Reviewed-by: Adam Jackson <[email protected]>
* mesa: Make gl_vertex_array contain pointers to first order VAO members.Mathias Fröhlich2018-03-105-115/+149
| | | | | | | | | | | | | | | Instead of keeping a copy of the vertex array content in struct gl_vertex_array only keep pointers to the first order information originaly in the VAO. For that represent the current values by struct gl_array_attributes and struct gl_vertex_buffer_binding. v2: Change comments. Remove gl... prefix from variables except in the i965 directory where it was like that before. Reindent because of that. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* i965: Hard code CS scratch_ids_per_subslice for CherryviewJordan Justen2018-03-091-17/+27
| | | | | | | | | | | | | Ken suggested that we might be underallocating scratch space on HD 400. Allocating scratch space as though there was actually 8 EUs seems to help with a GPU hang seen on synmark CSDof. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104636 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105290 Cc: <[email protected]> Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Tested-by: Eero Tamminen <[email protected]>
* i965: perf: consolidate unmapping oa perf bo outside accumulationLionel Landwerlin2018-03-081-4/+3
| | | | | | | | | Do this in one place outside the only caller of the accumulation function. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: perf: count number of accumlated reportsLionel Landwerlin2018-03-081-0/+6
| | | | | | | | This will be reused later. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: perf: reuse timescale base function from queryLionel Landwerlin2018-03-081-11/+2
| | | | | | | | We already have the same function in brw_queryobj.c Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: perf: store sysfs device entry into contextLionel Landwerlin2018-03-082-76/+73
| | | | | | | | We want to reuse it later on. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: perf: store the hw_id of the context in the queryLionel Landwerlin2018-03-081-6/+11
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: perf: default case for unknown query typesLionel Landwerlin2018-03-081-1/+31
| | | | | | | | Just some extra safety before further changes. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel: Add missing includes for building on AndroidClayton Craft2018-03-061-0/+1
| | | | | | | | | | | This adds a missing library to the i965/Android.mk file, and updates intel/Android.mk to include the new library. Without this, mesa does not build on Android. Fixes: 272bef0601a "intel: Split gen_device_info out into libintel_dev" Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Drop SURFACE_FORMAT enum from genxml.Kenneth Graunke2018-03-051-4/+4
| | | | | | | | | | | We want people to be using ISL_FORMAT_*, rather than the genxml format enumerations. This patch drops 10 separate copies, and drops a bunch of ugly casting. Reviewed-by: Jordan Justen <[email protected]> [[email protected]: Minor changes for rebase] Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* intel: Split gen_device_info out into libintel_devJordan Justen2018-03-055-4/+6
| | | | | | | | | | | | Split out the device info so isl doesn't depend on intel/common. Now it will depend on the new intel/dev device info lib. This will allow the decoder in intel/common to use isl, allowing us to apply Ken's patch that removes the genxml duplication of surface formats. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* i965: Silence unused parameter warnings in genX_state_uploadIan Romanick2018-03-021-20/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reduces my build from 1772 warnings to 1717 warnings by silencing 55 instances of things like ../../SOURCE/master/src/mesa/drivers/dri/i965/genX_state_upload.c: In function ‘gen4_emit_vertex_buffer_state’: ../../SOURCE/master/src/mesa/drivers/dri/i965/genX_state_upload.c:313:41: warning: unused parameter ‘end_offset’ [-Wunused-parameter] unsigned end_offset, ^~~~~~~~~~ ../../SOURCE/master/src/mesa/drivers/dri/i965/genX_state_upload.c: In function ‘gen4_emit_sampler_state_pointers_xs’: ../../SOURCE/master/src/mesa/drivers/dri/i965/genX_state_upload.c:4689:58: warning: unused parameter ‘brw’ [-Wunused-parameter] genX(emit_sampler_state_pointers_xs)(struct brw_context *brw, ^~~ ../../SOURCE/master/src/mesa/drivers/dri/i965/genX_state_upload.c:4690:62: warning: unused parameter ‘stage_state’ [-Wunused-parameter] struct brw_stage_state *stage_state) ^~~~~~~~~~~ ../../SOURCE/master/src/mesa/drivers/dri/i965/genX_state_upload.c: In function ‘gen4_upload_default_color’: ../../SOURCE/master/src/mesa/drivers/dri/i965/genX_state_upload.c:4730:40: warning: unused parameter ‘format’ [-Wunused-parameter] mesa_format format, GLenum base_format, ^~~~~~ ../../SOURCE/master/src/mesa/drivers/dri/i965/genX_state_upload.c: In function ‘translate_wrap_mode’: ../../SOURCE/master/src/mesa/drivers/dri/i965/genX_state_upload.c:4906:41: warning: unused parameter ‘brw’ [-Wunused-parameter] translate_wrap_mode(struct brw_context *brw, GLenum wrap, bool using_nearest) ^~~ ../../SOURCE/master/src/mesa/drivers/dri/i965/genX_state_upload.c: In function ‘gen4_update_sampler_state’: ../../SOURCE/master/src/mesa/drivers/dri/i965/genX_state_upload.c:4972:37: warning: unused parameter ‘batch_offset_for_sampler_state’ [-Wunused-parameter] uint32_t batch_offset_for_sampler_state) ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* i965: Silence unused parameter warnings in blorpIan Romanick2018-03-022-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reduces my build from 2023 warnings to 1960 warnings by silencing 63 instances of things like In file included from ../../SOURCE/master/src/mesa/drivers/dri/i965/genX_blorp_exec.c:33:0: ../../SOURCE/master/src/intel/blorp/blorp_genX_exec.h: In function ‘blorp_emit_cc_viewport’: ../../SOURCE/master/src/intel/blorp/blorp_genX_exec.h:500:51: warning: unused parameter ‘params’ [-Wunused-parameter] const struct blorp_params *params) ^~~~~~ ../../SOURCE/master/src/intel/blorp/blorp_genX_exec.h: In function ‘blorp_emit_sampler_state’: ../../SOURCE/master/src/intel/blorp/blorp_genX_exec.h:524:53: warning: unused parameter ‘params’ [-Wunused-parameter] const struct blorp_params *params) ^~~~~~ In file included from ../../SOURCE/master/src/mesa/drivers/dri/i965/genX_blorp_exec.c:36:0: ../../SOURCE/master/src/mesa/drivers/dri/i965/gen4_blorp_exec.h: In function ‘blorp_emit_vs_state’: ../../SOURCE/master/src/mesa/drivers/dri/i965/gen4_blorp_exec.h:50:48: warning: unused parameter ‘params’ [-Wunused-parameter] const struct blorp_params *params) ^~~~~~ ../../SOURCE/master/src/mesa/drivers/dri/i965/genX_blorp_exec.c: In function ‘blorp_flush_range’: ../../SOURCE/master/src/mesa/drivers/dri/i965/genX_blorp_exec.c:197:39: warning: unused parameter ‘batch’ [-Wunused-parameter] blorp_flush_range(struct blorp_batch *batch, void *start, size_t size) ^~~~~ ../../SOURCE/master/src/mesa/drivers/dri/i965/genX_blorp_exec.c:197:52: warning: unused parameter ‘start’ [-Wunused-parameter] blorp_flush_range(struct blorp_batch *batch, void *start, size_t size) ^~~~~ ../../SOURCE/master/src/mesa/drivers/dri/i965/genX_blorp_exec.c:197:66: warning: unused parameter ‘size’ [-Wunused-parameter] blorp_flush_range(struct blorp_batch *batch, void *start, size_t size) ^~~~ Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* i965: Silence unused parameter warnings in generated OA codeIan Romanick2018-03-021-1/+1
| | | | | | | | | | | | | | Reduces my build from 6301 warnings to 2075 warnings by silencing 4226 instances of things like src/mesa/drivers/dri/i965/i965@sta/brw_oa_hsw.c: In function ‘hsw__render_basic__gpu_core_clocks__read’: src/mesa/drivers/dri/i965/i965@sta/brw_oa_hsw.c:41:62: warning: unused parameter ‘brw’ [-Wunused-parameter] hsw__render_basic__gpu_core_clocks__read(struct brw_context *brw, ^~~ Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* i965: Silence unused parameter warningsIan Romanick2018-03-021-1/+1
| | | | | | | | | | | | | | | Reduces my build from 7119 warnings to 7005 warnings by silencing 114 instances of In file included from ../../SOURCE/master/src/mesa/drivers/dri/i965/brw_context.h:46:0, from ../../SOURCE/master/src/mesa/drivers/dri/i965/intel_pixel_read.c:38: ../../SOURCE/master/src/mesa/drivers/dri/i965/brw_bufmgr.h: In function ‘brw_bo_unmap’: ../../SOURCE/master/src/mesa/drivers/dri/i965/brw_bufmgr.h:258:47: warning: unused parameter ‘bo’ [-Wunused-parameter] static inline int brw_bo_unmap(struct brw_bo *bo) { return 0; } ^~ Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* i965: Mark upload buffers with MAP_ASYNC and MAP_PERSISTENT.Kenneth Graunke2018-03-021-1/+3
| | | | | | | | | This should have no practical impact. For the default uploader, we don't really care, but for others, we may want to append more data as the GPU is reading existing data, which means we need async and persistent flags. Reviewed-by: Chris Wilson <[email protected]>
* i965: Generalize intel_upload.c to support multiple uploaders.Kenneth Graunke2018-03-029-91/+101
| | | | | | | | | | | | | I'd like to reuse the upload logic for a new program cache, but the buffers will need to have a different lifetime than the default uploader, and also some address space restrictions. So, we can't use a single uploader for both situations - we'll need two of them. This creates a public 'uploader' structure, and adjusts the interface to take an uploader rather than always using brw->upload. It should have no functional change at the moment. Reviewed-by: Chris Wilson <[email protected]>
* i965: Allow 48-bit addressing on Gen8+.Kenneth Graunke2018-03-017-18/+127
| | | | | | | | | | | | | | | | | This allows most GPU objects to use the full 48-bit address space offered by Gen8+ platforms, rather than being stuck with 32-bit. This expands the available GPU memory from 4G to 256TB or so. A few objects - instruction, scratch, and vertex buffers - need to remain pinned in the low 4GB of the address space for various reasons. We default everything to 48-bit but disable it in those cases. Thanks to Jason Ekstrand for blazing this trail in anv first and finding the nasty undocumented hardware issues. This patch simply rips off all of his findings. Reviewed-by: Jordan Justen <[email protected]> Acked-by: Jason Ekstrand <[email protected]>
* i965: Shorten the name of the workaround BO.Kenneth Graunke2018-03-011-3/+1
| | | | | This makes the name shorter in debug printouts. If "workaround_bo" is good enough for the code, it's probably good enough for debugging.
* i965: Add debugging code to dump the validation list.Kenneth Graunke2018-03-011-0/+22
| | | | | When anything goes wrong with this code, dumping the validation list is a useful way to figure out what's happening.
* i965: Fix RELOC_WRITE typo in brw_store_data_imm64()Andriy Khulap2018-03-011-1/+1
| | | | | | | | | | Fixes: 6c530ad11605 ("i965: Reduce passing 2x32b of reloc_domains to 2 bits") Signed-off-by: Andriy Khulap <[email protected]> Signed-off-by: Vadym Shovkoplias <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/sbe: fix number of inputs for active componentsIago Toral Quiroga2018-03-011-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In 16631ca30ea6 we fixed gen9 active components to account for padded inputs in the URB, which we can have with SSO programs. To do that, instead of going through the bitfield of inputs (which doesn't include padding information), we compute the number of inputs from the size of the URB entry. Unfortunately, there are some special inputs that are not stored in the URB and that we also need to account for. These special inputs are identified and handled during calculate_attr_overrides(). Instead of keeping track of the exact number of inputs, we just program active components for all possible inputs like we do in anvil. This fixes a regression in a WebGL program that uses Point Sprite functionality (specifically, VARYING_SLOT_PNTC). v2: - Add 'Fixes' tag (Mark Janes) - make no_vue_inputs int instead of uint32_t, and add const qualifier to num_inputs variable (Ian) v3: - Do not try to count inputs correctly, just program all input slots like we do in anvil (Ken) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105224 Fixes: 16631ca30ea6 (i965/sbe: fix active components for SSO programs with over 16 inputs) Reviewed-by: Kenneth Graunke <[email protected]>
* Revert "i965: Only emit 3DSTATE_DRAWING_RECTANGLE once on gen8+"Mark Janes2018-02-283-13/+2
| | | | | | | | | | | | | This reverts commit a2c1e48f15995a826dc759e064c2603882a37e0c. On BDWGT3e and KBLGT3e systems, this commit regressed the following tests: piglit.spec.ext_framebuffer_multisample.accuracy 2 stencil_resolve small depthstencil piglit.spec.ext_framebuffer_multisample.accuracy 4 stencil_resolve small depthstencil piglit.spec.ext_framebuffer_multisample.accuracy 6 stencil_resolve small depthstencil piglit.spec.ext_framebuffer_multisample.accuracy 8 stencil_resolve small depthstencil piglit.spec.ext_framebuffer_multisample.accuracy all_samples stencil_resolve small depthstencil
* i965: Only emit 3DSTATE_DRAWING_RECTANGLE once on gen8+Jason Ekstrand2018-02-283-2/+13
| | | | | Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Be more clever about setting up our viewport clipJason Ekstrand2018-02-281-8/+12
| | | | | | | | | | | | Before, we were trusting in the hardware to take the intersection of the viewport clip with the drawing rectangle. Unfortunately, 3DSTATE_DRAWING_RECTANGLE is fairly expensive because it implicitly does a full pipeline stall. If we're a bit more careful with our viewport clipping, we can just re-emit it once at context creation time. Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Disable 64-bit extensions on platforms without 64-bit typesMatt Turner2018-02-281-4/+5
| | | | | | | | Gen11 does not support DF, Q, UQ types in hardware. As a result, we have to disable some GL extensions until they can be reimplemented. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965: Warn about preliminary support for Gen11Matt Turner2018-02-281-0/+7
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: use context priority definitions from gen_defines.hTapani Pälli2018-02-283-10/+10
| | | | | | Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965: Use gen_get_pci_device_id_overrideJordan Justen2018-02-271-52/+5
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Scott D Phillips <[email protected]>
* glsl: Specify framebuffer fetch coherency mode in ↵Francisco Jerez2018-02-241-1/+2
| | | | | | | | | | | | | | | | | | | | | lower_blend_equation_advanced(). This requires passing an extra argument to the lowering pass because the KHR_blend_equation_advanced specification doesn't seem to define any mechanism for the implementation to determine at compile-time whether coherent blending can ever be used (not even an "#extension KHR_blend_equation_advanced_coherent" directive seems to be required in the shader source AFAICT). In the long run we'll probably want to do state-dependent recompiles based on the value of ctx->Color.BlendCoherent, but right now there would be no benefit from that because the only driver that supports coherent framebuffer fetch is i965 on SKL+ hardware, which are unable to support the non-coherent path for the moment because of texture layout issues, so framebuffer fetch coherency is always enabled for them. Reviewed-by: Plamena Manolova <[email protected]>
* mesa: Rename MESA_shader_framebuffer_fetch gl_extensions bits to EXT.Francisco Jerez2018-02-245-7/+7
| | | | | | | | The changes I had originally planned for the MESA_shader_framebuffer_fetch extension have been merged into the EXT spec, there's no point in keeping MESA_shader_framebuffer_fetch extension enables. Reviewed-by: Plamena Manolova <[email protected]>
* mesa: Rename dd_function_table::BlendBarrier to match latest EXT spec.Francisco Jerez2018-02-241-2/+2
| | | | | | | | This GL entry point was renamed to glFramebufferFetchBarrier() in the EXT extension on request from Khronos members. Update the Mesa codebase to match the latest spec. Reviewed-by: Plamena Manolova <[email protected]>
* i965: Fix KHR_blend_equation_advanced with some render targets.Francisco Jerez2018-02-241-1/+3
| | | | | | | | | | | | | | | | This reverts two bogus and seemingly useless changes from the commits referenced below, which broke KHR_blend_equation_advanced (and EXT_shader_framebuffer_fetch_non_coherent which wasn't exposed yet) for any kind of render target surface that would cause the get_isl_surf() call in brw_emit_surface_state() to do anything useful (notice how the result of get_isl_surf() is completely ignored by the caller right now), as was the case while using those extensions with 1D array or 3D framebuffers in particular. Fixes: f5859b45b1686e8116380d87 "i965/miptree: Switch remaining surfaces to isl" Fixes: bf24c3539e4b6989512968ca "i965/miptree: Clean-up unused" Cc: [email protected] Reviewed-by: Plamena Manolova <[email protected]>
* mesa: expose ARB_enhanced_layouts in the compatibility profileMarek Olšák2018-02-231-1/+2
| | | | | | | GLSL 1.40 is required. Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: enable OpenGL 3.1 with ARB_compatibilityMarek Olšák2018-02-231-8/+0
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: Add flush_vertices to _mesa_bind_vertex_buffer.Mathias Fröhlich2018-02-231-7/+9
| | | | | | | We will need the flush_vertices argument later in this series. Signed-off-by: Mathias Fröhlich <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: Add flush_vertices to _mesa_{enable,disable}_vertex_array_attrib.Mathias Fröhlich2018-02-231-7/+11
| | | | | | | We will need the flush_vertices argument later in this series. Signed-off-by: Mathias Fröhlich <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: Provide an alternative to get_vp_mode()Mathias Fröhlich2018-02-231-0/+2
| | | | | | | | | | | | | | | | | To get equivalent information than get_vp_mode(), track the vertex processing mode in a per context variable at gl_vertex_program_state::_VPMode. This aims to replace get_vp_mode() as seen in the vbo module. But instead of the get_vp_mode() implementation which only gives correct answers past calling _mesa_update_state() this context variable is immediately tracked when the vertex processing state is modified. The correctness of this value is asserted on state validation. With this in place we should be able to untangle the dependency with varying_vp_inputs and state invalidation. Signed-off-by: Mathias Fröhlich <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* i965: perf: ensure reading config IDs from sysfs isn't interruptedLionel Landwerlin2018-02-231-1/+2
| | | | | | | Fixes: 458468c136e "i965: Expose OA counters via INTEL_performance_query" Signed-off-by: Lionel Landwerlin <[email protected]> Cc: <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* i965: Use finish_external instead of make_shareable in setTexBuffer2Jason Ekstrand2018-02-215-2/+87
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The setTexBuffer2 hook from GLX is used to implement glxBindTexImageEXT which has tighter restrictions than just "it's shared". In particular, it says that any rendering to the image while it is bound causes the contents to become undefined. The GLX_EXT_texture_from_pixmap extension provides us with an acquire and release in the form of glXBindTexImageEXT and glXReleaseTexImageEXT. The extension spec says, "Rendering to the drawable while it is bound to a texture will leave the contents of the texture in an undefined state. However, no synchronization between rendering and texturing is done by GLX. It is the application's responsibility to implement any synchronization required." From the EGL 1.4 spec for eglBindTexImage: "After eglBindTexImage is called, the specified surface is no longer available for reading or writing. Any read operation, such as glReadPixels or eglCopyBuffers, which reads values from any of the surface’s color buffers or ancillary buffers will produce indeterminate results. In addition, draw operations that are done to the surface before its color buffer is released from the texture produce indeterminate results In other words, between the bind and release calls, we effectively own those pixels and can assume, so long as we don't crash, that no one else is reading from/writing to the surface. The GLX and EGL implementations call the setTexBuffer2 and releaseTexBuffer function pointers that the driver can hook. In theory, this means that, between BindTexImage and ReleaseTexImage, we own the pixels and it should be safe to track aux usage so we can avoid redundant resolves so long as we start off with the right assumption at the start of the bind/release pair. In practice, however, X11 has slightly different expectations. It's expected that the server may be drawing to the image at the same time as the compositor is texturing from it. In that case, the worst expected outcome should be tearing or partial rendering and not random corruption like we see when rendering races with scanout with CCS. Fortunately, the GEM rules about texture/render dependencies save us here. If X11 submits work to write to a pixmap after the compositor has submitted work to texture from it, GEM inserts a dependency between the compositor and X11. If X11 is using a high-priority context, this will cause the compositor to get a temporarily boosted priority while the batch from X11 is waiting on it. This means that we will never have an actual race between X11 and the compositor so no corruption can happen. Unfortunately, however, this means that X11 will likely be rendering to it between the compositor's BindTexImage and ReleaseTexImage calls. If we want to avoid strange issues, we need to be a bit careful about resolves because we can't really transition it away from the "default" aux usage. The only case where this would practically be a problem is with image_load_store where we have to do a full resolve in order to use the image via the data port. Even there it would only be a problem if batches were split such that X11's rendering happens between the resolve and the use of it as a storage image. However, the chances of this happening are very slim so we just emit a warning and hope for the best. This commit adds a new helper intel_miptree_finish_external which resets all aux state to whatever ISL says is the right worst-case "default" for the given modifier. It feels a little awkward to call it "finish" because it's actually an acquire from the perspective of the driver, but it matches the semantics of the other prepare/finish functions. This new helper gets called in intelSetTexBuffer2 instead of make_shareable. We also add an intelReleaseTexBuffer (we passed NULL to releaseTexBuffer before) and call intel_miptree_prepare_external in it. This probably does nothing most of the time but it means that the prepare/finish calls are properly matched. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/tex_image: Reference the renderbuffer miptree in setTexBuffer2Jason Ekstrand2018-02-211-14/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | The old code made a new miptree that referenced the same BO as the renderbuffer and just trusted in the memory aliasing to work. There are only two ways in which the new miptree is liable to differ from the one in the renderbuffer and neither of them matter: 1) It may have a different target. The only targets that we can ever see in intelSetTexBuffer2 are GL_TEXTURE_2D and GL_TEXTURE_RECTANGLE and the difference between the two doesn't matter as far as the miptree is concerned; genX(update_sampler_state) only looks at the gl_texture_object and not the miptree when determining whether or not to use normalized coordinates. 2) It may have a very slightly different format. Again, this doesn't matter because we've supported texture views for quite some time so we always look at the gl_texture_object format instead of the miptree format for hardware setup anyway. On the other hand, because we were recreating the miptree, we were using intel_miptree_create_for_bo which doesn't understand modifiers. We really want this function to work without doing a resolve so long as you have modifiers so we need to fix that. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/tex_image: Pull the tex format from the renderbuffer in intelSetTexBuffer2Jason Ekstrand2018-02-211-15/+19
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/miptree: Loosen the format check in miptree_match_imageJason Ekstrand2018-02-214-6/+8
| | | | | | | | | | This function is used to determine when we need to re-allocate a miptree. Since we do nothing different in miptree allocation for sRGB vs. linear, loosening this should be safe and may lead to less copying and reallocating in some odd cases. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]>
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