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* radeon: Remove the non-libdrm kernel memory manager support.Eric Anholt2011-10-288-464/+2
| | | | We should have never been building this at this point.
* radeon: Insist on libdrm being present to build.Eric Anholt2011-10-283-98/+3
| | | | | | | There's no sense in building a broken driver. Previously, there was the potential of building a DRI1-only driver that would work for DRI1 and fail on DRI2 because the newer libdrm code wasn't present. Now the radeon build system should be matching intel and nouveau.
* dri: Remove driver GenerateMipmap hooks.Eric Anholt2011-10-284-67/+0
| | | | | Mesa sets up _mesa_meta_GenerateMipmap as the default hook, which does this check for fallback and call the fallback itself.
* radeon: Drop some remaining DRI1 vblank support code.Eric Anholt2011-10-283-58/+0
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* intel: remove dead prototype for old DRI1 code.Eric Anholt2011-10-281-5/+0
| | | | Noticed while grepping for radeon code.
* radeon: Simplify cliprects computation now that there's just 1.Eric Anholt2011-10-283-69/+15
| | | | | | This can probably be reduced even further by moving this logic to the scissor state update or just removing the logic entirely, but I don't trust myself in radeon quite that much.
* radeon: Drop the clipping in spans, now that we always have (0,0) -> (w,h).Eric Anholt2011-10-281-54/+38
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* radeon: Drop the legacy BO manager code.Eric Anholt2011-10-287-988/+0
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* radeon: Drop the DRI1 zero-copy TFP code.Eric Anholt2011-10-285-92/+0
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* radeon: Drop the radeon_cs_legacy code now that we rely on kernel mm.Eric Anholt2011-10-286-458/+0
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* radeon: Drop dri2 checks now that it's always true.Eric Anholt2011-10-2816-349/+0
| | | | This makes LOCK_HARDWARE empty, so it goes away.
* radeon: Drop the DRI1 swapbuffers implementation.Eric Anholt2011-10-283-294/+0
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* radeon: Drop the non-kernel-memory-manager support, and thus DRI1.Eric Anholt2011-10-2813-711/+112
| | | | | | | | | | It's past time, and it was going to get in the way of the renderbuffer mapping refactor. We dropped all the other DRI1 drivers for this release, and I can't imagine anybody supporting DRI1 radeon classic in a new release of Mesa. Diff produced by treating kernel_mm as true, deleting the DRI1 paths that produce kernel_mm false, and deleting code.
* r200: Drop the non-kernel-memory-manager and DRI1 code.Eric Anholt2011-10-286-528/+86
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* radeon: Unifdef RADEON_R300 and RADEON_R600.Eric Anholt2011-10-283-636/+6
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* r300c, r600c: Remove these DRI drivers.Eric Anholt2011-10-28183-56328/+0
| | | | | | | | | They have been superseded by the gallium equivalents. Acked-by: Michel Dänzer <[email protected]> Acked-by: Alex Deucher <[email protected]> Acked-by: Dave Airlie <[email protected]> Acked-by: Corbin Simpson <[email protected]>
* radeon: Delete DRI1 screen init code and thus support for !kernel_mm.Eric Anholt2011-10-281-495/+5
| | | | | | | | | | | It's past time, and it was going to get in the way of the renderbuffer mapping refactor. We dropped all the other DRI1 drivers for this release, and I can't imagine anybody supporting DRI1 radeon classic in a new release of Mesa. Cleanup of the resulting dead code to follow. Acked-by: Alex Deucher <[email protected]>
* dri: Drop _dri_texformats that just obfuscate MESA_FORMAT names.Eric Anholt2011-10-283-10/+3
| | | | | The remaining _dri_texformats are the ones that are variable depending on the endianness of the system.
* radeon: Use _mesa_get_format_base_format for winsys renderbuffer setup.Eric Anholt2011-10-281-10/+1
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* radeon: Remove dead swrast renderbuffer setup code.Eric Anholt2011-10-281-29/+20
| | | | This was from the stub code in the initial commit of this file.
* i965/gen6+: Add support for noperspective interpolation.Paul Berry2011-10-279-39/+122
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This required the following changes: - WM setup now makes the appropriate set of barycentric coordinates (perspective vs. noperspective) available to the fragment shader, based on whether the shader requires perspective interpolation, noperspective interpolation, both, or neither. - The fragment shader backend now uses the appropriate set of barycentric coordiantes when interpolating, based on the interpolation mode returned by ir_variable::determine_interpolation_mode(). - SF setup now uses gl_fragment_program::InterpQualifier to determine which attributes are to be flat shaded (as opposed to the old logic, which only flat shaded colors). - CLIP setup now ensures that the clipper outputs non-perspective barycentric coordinates when they are needed by the fragment shader. Fixes the remaining piglit tests of interpolation qualifiers that were failing: - interpolation-flat-*-smooth-none - interpolation-flat-other-flat-none - interpolation-noperspective-* - interpolation-smooth-gl_*Color-flat-* Reviewed-by: Eric Anholt <[email protected]>
* i965/gen6+: Rename GEN6_CLIP_BARYCENTRIC_ENABLE.Paul Berry2011-10-271-1/+1
| | | | | | | | | | The name was misleading. The actual effect of the bit is to cause the clipper to emit *non-perspective* barycentric coordinate information (which is only needed when doing noperspective interpolation). Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965/fs: use determine_interpolation_mode().Paul Berry2011-10-271-4/+4
| | | | | | | | | | | | | | This patch changes how fs_visitor::emit_general_interpolation() decides what kind of interpolation to do. Previously, it used the shade model to determine how to interpolate colors, and used smooth interpolation on everything else. Now it uses ir_variable::determine_interpolation_mode(), so that it respects GLSL 1.30 interpolation qualifiers. Fixes piglit tests interpolation-flat-*-smooth-{distance,fixed,vertex} and interpolation-flat-other-flat-{distance,fixed,vertex}. Reviewed-by: Eric Anholt <[email protected]>
* i965/gen6+: Parameterize barycentric interpolation modes.Paul Berry2011-10-2710-38/+103
| | | | | | | | | | | | | | | | | This patch modifies the fragment shader back-end so that instead of using a single delta_x/delta_y register pair to store barycentric coordinates, it uses an array of such register pairs, one for each possible intepolation mode. When setting up the WM, we intstruct it to only provide the barycentric coordinates that are actually needed by the fragment shader--that is computed by brw_compute_barycentric_interp_modes(). Currently this function returns just BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC, because this is the only interpolation mode we support. However, that will change in a later patch. Reviewed-by: Eric Anholt <[email protected]>
* i965/fs: Fix split_virtual_grfs() when delta_xy not in a virtual register.Paul Berry2011-10-271-1/+1
| | | | | | | | | | | | | | This patch modifies the special case in fs_visitor::split_virtual_grfs() that prevents splitting from being applied to the delta_x/delta_y register pair (this register pair needs to remain contiguous so that it can be used by the PLN instruction). When gen>=6, this register pair is in a fixed location, not a virtual register, so it was in no danger of being split. And split_virtual_grfs' attempt not to split it was preventing some other unrelated register from being split. Reviewed-by: Eric Anholt <[email protected]>
* intel: Drop texture border support code.Eric Anholt2011-10-265-93/+29
| | | | | | | | | | Now that texture borders are gone, we never need to allocate our textures through non-miptrees, which simplifies some irritating paths. v2: Remove the !mt support case from intel_map_texture_image() Reviewed-by: Kenneth Graunke <[email protected]> (v1) Reviewed-by: Brian Paul <[email protected]>
* intel: Enable stripping of texture borders.Eric Anholt2011-10-261-0/+2
| | | | | | | | | | | | | | | | | | | This replaces software rendering of textures with the deprecated 1-pixel border (which is always bad, since mipmapping is rather broken in swrast, and GLSL 1.30 is unsupported) with hardware rendering that just pretends there was never a border (so you have potential seams on apps that actually intentionally used the 1-pixel borders, but correct rendering otherwise). This doesn't regress any piglit tests on gen6 (since the texwrap border/bordercolor cases already failed due to broken border color handling), but regresses texwrap border cases on original gen4 since those end up sampling the border color instead of the border pixels. It's a small price to pay for not thinking about texture borders any more. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* glsl: Add uniform_locations_assigned parameter to do_dead_code opt passIan Romanick2011-10-251-1/+2
| | | | | | | | | | | | | | | | | Setting this flag prevents declarations of uniforms from being removed from the IR. Since the IR is directly used by several API functions that query uniforms in shaders, uniform declarations cannot be removed after the locations have been set. However, it should still be safe to reorder the declarations (this is not tested). Signed-off-by: Ian Romanick <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=41980 Tested-by: Brian Paul <[email protected]> Reviewed-by: Bryan Cain <[email protected]> Cc: Vinson Lee <[email protected]> Cc: José Fonseca <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Yuanhan Liu <[email protected]>
* i965: Add more #defines for Gen6+ 3DSTATE_GS fields.Kenneth Graunke2011-10-251-0/+8
| | | | | | | These should be useful for doing transform feedback on Sandybridge. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Add new brw_context::max_gs_threads constant.Kenneth Graunke2011-10-252-0/+8
| | | | | | | | These are correct to the best of my knowledge, gleaned from a variety of internal sources. Sadly, the Sandybridge PRM has incorrect limits. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Rename (vs|wm)_max_threads to max_(vs|wm)_threads for consistency.Kenneth Graunke2011-10-2510-24/+29
| | | | | | | | | The inconsistency between vs_max_threads and max_vs_entries was rather annoying. I could never seem to remember which one was reversed, which made it harder to find quickly. "Max __ Threads" seems more natural. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Remove "single threaded" INTEL_DEBUG mode.Kenneth Graunke2011-10-255-18/+4
| | | | | | | | | | | | | | | | | According to the docs for 3DSTATE_PS (Gen7+) and 3DSTATE_WM (Gen6), there is a platform dependent value for the minimum number of pixel shader threads. It may also vary based on whether WIZ Hashing is on. For example, Ivybridge requires at least 4 threads if WIZ hashing is disabled, and 8 if it's enabled. Programming it to use less threads is illegal. Sandybridge appears to have similar restrictions. So on newer platforms, INTEL_DEBUG=sing will probably just hang the GPU. Rather than try to patch it up for newer platforms and extend it to support geometry shaders, just remove it as it isn't that useful anyway. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* intel: Kill dead code in intel_miptree_copy_teximage()Chad Versace2011-10-251-59/+28
| | | | | | | | | | | | | Kill the code paths taken when src_mt is null. It is never null, otherwise there would be a segfault on line 4 of this function: GLuint width = src_mt->level[level].width; (Some interleaved lines in the diff make the real diff non-obvious. All I did was delete some code and then left-shifted what remained to correct the indentation.) Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* i965: Apply post-sync non-zero workaround to homebrew workaround.Kenneth Graunke2011-10-241-0/+2
| | | | | | | | | | | | | | | | | | In commit 3e5d3626, Eric added a homebrew workaround to fix GPU hangs in the Mesa "engine" demo and oglc's api-texcoord test. Unfortunately, his PIPE_CONTROL contains a Depth Stall, which necessitates the post-sync non-zero workaround, Fixes GPU hangs in Civilization 4, PlaneShift, and 3DMMES. Hopefully Heroes of Newerth as well, though I haven't tested that. NOTE: This is candidate for the 7.11 branch. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=40324 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=41096 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-and-tested-by: Eric Anholt <[email protected]>
* intel: remove duplicated #include of texstore.hBrian Paul2011-10-231-1/+0
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* radeon: remove unnecessary #includes of texstore.hBrian Paul2011-10-234-4/+0
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* mesa: add swrast_texture_image::BufferBrian Paul2011-10-232-12/+12
| | | | | | | | | | | | | | | In the past, swrast_texture_image::Data has been overloaded. It could either point to malloc'd memory storing texture data, or it could point to a current mapping of GPU memory. Now, Buffer always points to malloc'd memory (if we're not using GPU memory) and Data always points to mapped memory. The next step would be to rename Data -> Map. This change also involves adding swrast functions for mapping textures and renderbuffers prior to rendering to setup the Data pointer. Plus, corresponding functions to unmap texures and renderbuffers. This is very much like similar code in the dri drivers.
* mesa: remove _mesa_alloc_texmemory(), _mesa_free_texmemory()Brian Paul2011-10-235-7/+9
| | | | Core Mesa no longer does any texture memory allocation.
* mesa: move gl_texture_image::Data, RowStride, ImageOffsets to swrastBrian Paul2011-10-2314-107/+116
| | | | | | Only swrast and the drivers that fall back to swrast need these fields now. This removes the last of the fields related to software rendering from gl_texture_image.
* i965: Set MaxIfDepth to UINT_MAX on Gen6+ and 16 on prior generations.Kenneth Graunke2011-10-211-0/+1
| | | | | | | | | | | | | Commit 488fe51cf823ccd137c667f1e92dd86f8323b723 converted the EmitNoIfs flag to MaxIfDepth, an unsigned integer saying "flatten if-statements nested beyond this depth." Unfortunately, i965 left this initialized to 0, which made ir_to_mesa attempt to flatten all if-statements. We didn't notice right away because we usually throw away ir_to_mesa's code in favor of the native VS and FS backends...but this still creates a lot of unnecessary work. Signed-off-by: Kenneth Graunke <[email protected]>
* i965: Remove copy and pasted gen7_wm_constants state atom.Kenneth Graunke2011-10-202-56/+1
| | | | | | | Now that this is identical to gen6_wm_constants, just use that instead. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Use AUB_TRACE_WM_CONSTANTS in gen7_prepare_wm_push_constants.Kenneth Graunke2011-10-201-1/+1
| | | | | | | | This makes it match gen6_prepare_wm_push_constants. For some reason, it had been using AUB_TRACE_NO_TYPE. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Fix incorrect dirty bit in gen6_prepare_wm_push_constants.Kenneth Graunke2011-10-201-2/+2
| | | | | | | | | We definitely want CACHE_NEW_WM_PROG, not CACHE_NEW_VS_PROG. NOTE: This is a candidate for the 7.11 branch. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965/vs: Fix comparisons with uint negation.Eric Anholt2011-10-203-0/+32
| | | | | | | | | | The condmod instruction ends up generating garbage condition codes, because apparently the comparison happens on the accumulator value (33 bits for UD), not the truncated value that would be written. Fixes vs-op-neg-* Reviewed-by: Ian Romanick <[email protected]>
* i965/fs: Fix comparisions with uint negation.Eric Anholt2011-10-204-0/+49
| | | | | | | | | | The condmod instruction ends up generating garbage condition codes, because apparently the comparison happens on the accumulator value (33 bits for UD), not the truncated value that would be written. Fixes fs-op-neg-* Reviewed-by: Ian Romanick <[email protected]>
* i965: silence signed/unsigned comparison warningBrian Paul2011-10-191-1/+2
| | | | Reviewed-by: Paul Berry <[email protected]>
* i965: setup address rounding enable bitsYuanhan Liu2011-10-193-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | The patch(based on the reading of the emulator) came from while I was trying to fix the oglc pbo texImage.1PBODefaults fail. This case generates a texture with the width and height equal to window's width and height respectively, then try to texture it on the whole window. So, it's exactly one texel for one pixel. And, the min filter and mag filter are GL_LINEAR. It runs with swrast OK, as expected. But it failed with i965 driver. Well, you can't tell the difference from the screen, as the error is quite tiny. From my digging, it seems that there are some tiny error happened while getting tex address. This will break the one texel for one pixel rule in this case. Thus the linear result is taken, with tiny error. This patch would fix all oglc pbo subcase fail with the same issue on both ILK, SNB and IVB. v2: comments from Ian, make the address_round filed assignment consistent. (the sampler is alread memset to 0 by the xxx_update_samper_state caller, so need to assign 0 first) Signed-off-by: Yuanhan Liu <[email protected]>
* i915: make i830/i915_hiz_resolve_noop() staticBrian Paul2011-10-182-2/+2
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* i965: remove unused vars in brw_set_ff_sync_message()Brian Paul2011-10-181-3/+0
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* i965: Disassemble Ivybridge Data Port/Data Cache messages.Kenneth Graunke2011-10-181-0/+8
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
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