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* i965/iris: perf-queries: don't invalidate/flush 3d pipelineLionel Landwerlin2019-12-131-1/+9
* st/glsl_to_nir: use nir based program resource list builderTimothy Arceri2019-12-131-2/+2
* glsl: move nir_remap_dual_slot_attributes() call out of glsl_to_nir()Timothy Arceri2019-12-131-0/+8
* i965: Enable GL_EXT_gpu_shader4 on Gen6+Jason Ekstrand2019-12-121-0/+1
* intel/decoder: Make get_state_size take a full 64-bit address and a baseKenneth Graunke2019-12-101-3/+4
* blorp: Pass the VB size to the VF cache workaroundJason Ekstrand2019-12-051-0/+1
* mesa: Silence unused parameter warningIan Romanick2019-12-046-10/+10
* i965: update Makefile.sources for perf changesJonathan Gray2019-11-291-2/+0
* driconf, glsl: Add a vs_position_always_invariant optionKenneth Graunke2019-11-271-0/+3
* i965: Ensure that all 2101010 image imports can pass framebuffer completeness.Miguel Casas-Sanchez2019-11-191-2/+6
* Call shmget() with permission 0600 instead of 0777Brian Paul2019-11-181-1/+2
* intel/compiler: Add a flag to avoid compacting push constantsJason Ekstrand2019-11-181-0/+1
* i965: Unify CC_STATE and BLEND_STATE atoms on Haswell as a workaroundDanylo Piliaiev2019-11-181-2/+35
* i965/program_cache: Lift restriction on shader key sizeDanylo Piliaiev2019-11-121-12/+4
* Meson: Remove lib prefix from graw and osmesa when building with Mingw.Prodea Alexandru-Liviu2019-11-071-0/+2
* mesa: Prepare for the MESA_FORMAT_* enum to be sparse.Eric Anholt2019-11-071-0/+2
* util: rename PIPE_ARCH_*_ENDIAN to UTIL_ARCH_*_ENDIANDylan Baker2019-11-057-14/+14
* util/u_endian: set PIPE_ARCH_*_ENDIAN to 1Dylan Baker2019-11-057-14/+14
* dri/osmesa: use preprocessor for selecting endian code pathsDylan Baker2019-11-051-6/+9
* r100: Use preprocessor to select big vs little endian pathsDylan Baker2019-11-053-46/+51
* r200: use preprocessor for big vs little endian checksDylan Baker2019-11-052-45/+38
* radeon: replace xmlpool_options_h with idep_xmlconfig_headersEric Engestrom2019-10-311-2/+2
* r200: replace xmlpool_options_h with idep_xmlconfig_headersEric Engestrom2019-10-311-2/+2
* nouveau: replace xmlpool_options_h with idep_xmlconfig_headersEric Engestrom2019-10-311-2/+2
* i915: replace xmlpool_options_h with idep_xmlconfig_headersEric Engestrom2019-10-311-2/+2
* dri: replace xmlpool_options_h with idep_xmlconfig_headersEric Engestrom2019-10-311-2/+2
* intel: Support HIZ_CCS in isl_surf_get_ccs_surfNanley Chery2019-10-282-8/+8
* i965/miptree: Avoid -Wswitch for the Gen12 aux modesNanley Chery2019-10-281-0/+3
* util: rename list_empty() to list_is_empty()Timothy Arceri2019-10-281-1/+1
* i965: setup sized internalformat for MESA_FORMAT_R10G10B10A2_UNORMTapani Pälli2019-10-281-1/+9
* intel/perf: move registers to their own headerLionel Landwerlin2019-10-232-1/+2
* mesa: Redefine the RG formats as array formats.Eric Anholt2019-10-203-10/+10
* mesa: Replace MESA_FORMAT_L8A8/A8L8 UNORM/SNORM/SRGB with an array format.Eric Anholt2019-10-2010-27/+18
* mesa: Replace the LA16_UNORM packed formats with one array format.Eric Anholt2019-10-202-2/+5
* radeon: Drop the unused first arg of OUT_BATCH_RELOC.Eric Anholt2019-10-209-24/+24
* radeon: Fill in the TXOFFSET field containing the tile bits in our relocs.Eric Anholt2019-10-202-4/+5
* r100/r200: factor out txformat/txfilter setup from the TFP path.Eric Anholt2019-10-202-22/+10
* Revert "egl: Fixes transparency with EGL and X11."Hal Gentz2019-10-181-2/+0
* nir: support feeding state to nir_lower_clip_[vg]sErik Faye-Lund2019-10-171-1/+2
* nir: support lowering clipdist to arraysErik Faye-Lund2019-10-171-1/+1
* egl: Fixes transparency with EGL and X11.Hal Gentz2019-10-111-0/+2
* GL: drop symbols mangling supportEric Engestrom2019-10-102-8/+0
* nir: add a strip parameter to nir_serializeMarek Olšák2019-10-101-1/+1
* i965: Disable fast clears when running with INTEL_DEBUG=nofcCaio Marcelo de Oliveira Filho2019-10-092-0/+6
* meta: leak of shader program when decompressing tex-imagesSergii Romantsov2019-10-091-0/+1
* i965: Enable EXT_demote_to_helper_invocationCaio Marcelo de Oliveira Filho2019-09-301-0/+2
* intel: Increase Gen11 compute shader scratch IDs to 64.Kenneth Graunke2019-09-231-1/+13
* Revert "intel/gen11+: Enable Hardware filtering of Semi-Pipelined State in WM"Kenneth Graunke2019-09-232-9/+0
* Move blob from compiler/ to util/Jason Ekstrand2019-09-191-1/+1
* i965: support AYUV/XYUV for external import onlyHaihao Xiang2019-09-181-0/+2
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