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* i965/vec4: Calculate register allocation q values manually.Francisco Jerez2015-02-191-1/+17
| | | | | | | | | | | | This fixes a regression in the running time of Piglit introduced by commit 78e9043475d4bed8b50f7e413963c960fa0935bb, which increased the number of register allocation classes set up by the VEC4 back-end from 2 to 16. The algorithm used by ra_set_finalize() to calculate them is unnecessarily expensive, do it manually like the FS back-end does. Reported-by: Mark Janes <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Don't compact instructions with unmapped bits.Francisco Jerez2015-02-191-0/+53
| | | | | | | | | | | | | | | | | Some instruction bits don't have a mapping defined to any compacted instruction field. If they're ever set and we end up compacting the instruction they will be forced to zero. Avoid using compaction in such cases. v2: Align multiple lines of an expression to the same column. Change conditional compaction of 3-source instructions to an assertion. (Matt) v3: The 3-source instruction bit 105 is part of SourceIndex on CHV. Add assertion that reserved bit 7 is not set. (Matt) Document overlap with UIP and 64-bit immediate fields. v4: Make some more unmapped bit checks assertions. (Matt) Reviewed-by: Matt Turner <[email protected]>
* i965: Handle F16TO32/F32TO16 with dword src/dst consistently on both back-ends.Francisco Jerez2015-02-191-2/+12
| | | | | | | | | | | | | | Due to the way it's implemented in hardware, the F16TO32/F32TO16 instructions require the source/destination register to be of some 16-bit type in Align1 mode, while they require it to be some 32-bit type in Align16 mode (and as an undocumented feature the high 16 bits of the destination register are zeroed out in the case of the F32TO16 instruction on Gen7). Make their behaviour consistent so you can specify a 32 bit register type as source or destination and get predictable results in the most significant bits no matter what access mode is being used. Reviewed-by: Matt Turner <[email protected]>
* i965/gen8: Fix F32TO16 in vec4 mode if the source and destination registers ↵Francisco Jerez2015-02-191-9/+27
| | | | | | | | | | alias. We cannot zero out the destination register if it overlaps with the source. Use an Align1 instruction instead to zero out the high 16 bits after the conversion to half float. Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Replace ud_reg_to_w() with a more general helper function.Francisco Jerez2015-02-192-24/+25
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Don't attempt to reduce swizzles of send from GRF instructions.Francisco Jerez2015-02-191-1/+2
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Fix constant propagation across different types.Francisco Jerez2015-02-191-0/+10
| | | | | | | | | | If the source type differs from the original type of the constant we need to bit-cast it before propagating, otherwise the original type information will be lost. If the constant was a vector float there isn't much we can do, because the result of bit-casting the component values of a vector float cannot itself be represented as an immediate. Reviewed-by: Matt Turner <[email protected]>
* i965/simd8vs: Fix SIMD8 atomics (read-only)Jordan Justen2015-02-181-8/+16
| | | | | | | | | | | | | | | | An update for d9cd982d556be560af3bcbcdaf62b6b93eb934a5. A similar change was needed for CS to allow the piglit test tests/spec/arb_compute_shader/execution/simple-barrier-atomics.shader_test to pass. The previous change (d9cd982d) should fix cases that write atomics, such as atomicCounterIncrement, and this change will fix cases than only read atomics, such as atomicCounter. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Ben Widawsky <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i915: For the love of all that is holy, stop saying "IGD"Adam Jackson2015-02-181-7/+7
| | | | | | | a001 and a011 are pineview chips. Say so. Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Adam Jackson <[email protected]>
* i965: implement ARB_pipeline_statistics_queryBen Widawsky2015-02-173-0/+106
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NOTE: The implementation was initially one patch, this. All the history is kept here, even though all the core mesa changes were moved to the parent of this patch. This patch implements ARB_pipeline_statistics_query. This addition to GL does not add a new API. Instead, it adds new tokens to the existing query APIs. The work to hook up the new tokens is trivial due to it's similarity to the previous work done for the query APIs. I've implemented all the new tokens to some degree, but have stubbed out the untested ones at the entry point for Begin(). Doing this should allow the remainder of the code to be left in. The new tokens give GL clients a way to obtain stats about the GL pipeline. Generally, you get the number of things going in, invocations, and number of things coming out, primitives, of the various stages. There are two immediate uses for this, performance information, and debugging various types of misrendering. I doubt one can use these for debugging very complex applications, but for piglit tests, it should be quite useful. Tessellation shaders, and compute shaders are not addressed in this patch because there is no upstream implementation. I've implemented how I believe tessellation shader stats will work for Intel hardware (though there is a bit of ambiguity). Compute shaders are a bit more interesting though, and I don't yet know what we'll do there. For the lazy, here is a link to the relevant part of the spec: https://www.opengl.org/registry/specs/ARB/pipeline_statistics_query.txt Running the piglit tests http://lists.freedesktop.org/archives/piglit/2014-November/013321.html (http://cgit.freedesktop.org/~bwidawsk/piglit/log/?h=pipe_stats) yield the following results: > piglit-run.py -t stats tests/all.py output/pipeline_stats > [5/5] pass: 5 Running Test(s): 5 v2: - Don't allow pipeline_stats to be per stream (Ilia). This may (not sure) be needed for AMD_transform_feedback4, which we do not support. > If AMD_transform_feedback4 is supported then GEOMETRY_SHADER_PRIMITIVES_- > EMITTED_ARB counts primitives emitted to any of the vertex streams for > which STREAM_RASTERIZATION_AMD is enabled. - Remove comment from GL3.txt because it is only used for extensions that are part of required versions (Ilia) - Move the new tokens to a new XML doc instead of using the main GL4x.xml (Ilia) - Add a fallthrough comment (Ilia) - Only divide PS invocations by 4 on HSW+ (Ben) v3: - Add ARB_pipeline_statistics_query to relnotes.html - Add ARB_pipeline_statistics_query.xml to the Makefile.am, and master XML (Ilia) - Correct extension number (Ilia) - Add link to xml in the main GL API xml (Ilia) - remove special GS case from gen6_end_query (Ian) - Make lookup table static so gcc doesn't initialized it on every call (Ian) - Use if (_mesa_has_geometry_shaders(ctx)) instead of explicit checks (Ian) - Core mesa parts moved into a prep patch (Ilia) v4: - Change to 10.6 relnotes since we missed 10.5 window - Moved compute shader stuff into the switch statement (Jordan) - Jordan: Add compute shader support v5: - Fixed relnote style (Ilia) v6: - Rebased on master which beat me to adding the first relnotes - essentially this undoes v5 (which had a typo anyway) - Some code style fixes (Ken) - Remove some excess comments (Ken) - Unify tessellation failure style - unreachable (Ken) - Fix workaround comment for PS invocations (Ken) Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Prefer Meta over the BLT for BlitFramebuffer.Kenneth Graunke2015-02-171-7/+7
| | | | | | | | | | | | | | | | | There's some debate about whether we should use Meta or BLORP, but either should run circles around the BLT engine. In particular, this means that Gen8+ will use the 3D engine for blits, like we do on Gen6-7. Improves performance in "copypixrate -blit -back" (from Mesa demos) by 232.037% +/- 3.15795% (n=10) on Broadwell GT3e. v2: Rebase on Laura's changes. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Cc: "10.5" <[email protected]>
* i965/fs: Add algebraic optimizations for MAD.Matt Turner2015-02-171-0/+43
| | | | | | | | | total instructions in shared programs: 5764176 -> 5763808 (-0.01%) instructions in affected programs: 25121 -> 24753 (-1.46%) helped: 164 HURT: 2 Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Emit MAD instructions when possible.Matt Turner2015-02-172-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously we didn't emit MAD instructions since they cannot take immediate arguments, but with the opt_combine_constants() pass we can handle this properly. total instructions in shared programs: 5920017 -> 5733278 (-3.15%) instructions in affected programs: 3625153 -> 3438414 (-5.15%) helped: 22017 HURT: 870 GAINED: 91 LOST: 49 Without constant pooling, this patch is a complete loss: total instructions in shared programs: 5912589 -> 5987888 (1.27%) instructions in affected programs: 3190050 -> 3265349 (2.36%) helped: 1564 HURT: 17827 GAINED: 27 LOST: 101 And since the constant pooling patch by itself hurt a bunch of things, from before constant pooling to this patch the results are: total instructions in shared programs: 5895414 -> 5747946 (-2.50%) instructions in affected programs: 3617993 -> 3470525 (-4.08%) helped: 20478 HURT: 4469 GAINED: 54 LOST: 146 Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Allow immediates in MAD and LRP instructions.Matt Turner2015-02-172-3/+33
| | | | | | | | | | | | | | | And then the opt_combine_constants() pass will pull them out into registers. This will allow us to do some algebraic optimizations on MAD and LRP. total instructions in shared programs: 5946656 -> 5931320 (-0.26%) instructions in affected programs: 778247 -> 762911 (-1.97%) helped: 3780 HURT: 6 GAINED: 12 LOST: 12 Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Add pass to combine immediates.Matt Turner2015-02-174-0/+287
| | | | | | | | | | | | | total instructions in shared programs: 5885407 -> 5940958 (0.94%) instructions in affected programs: 3617311 -> 3672862 (1.54%) helped: 3 HURT: 23556 GAINED: 31 LOST: 165 ... but will allow us to always emit MAD instructions. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Remove force_writemask_all assertion for execsize < 8.Matt Turner2015-02-171-1/+0
| | | | | | | This doesn't seem to be necessary. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86974 Reviewed-by: Kenneth Graunke <[email protected]>
* i965/cfg: Add function to generate a dot file of the dominator tree.Matt Turner2015-02-172-0/+11
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/cfg: Add function to generate a dot file of the CFG.Matt Turner2015-02-172-0/+15
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/cfg: Calculate the immediate dominators.Matt Turner2015-02-172-4/+76
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/cfg: Allow cfg::dump to be called without a visitor.Matt Turner2015-02-171-1/+2
| | | | | | | | | The fs_visitor's dump_instruction() implementation calls cfg_t() indirectly through calculate_live_intervals, so if you have an infinite loop in the CFG code, you can't call cfg::dump(fs_visitor *) to debug it. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Allow exec_list sentinels as arguments to insert functions.Matt Turner2015-02-171-2/+4
| | | | | | | | | | | | | | | | | | To insert an instruction at the end of a basic block, we typically do something like inst = block->last_non_control_flow_inst(); inst->insert_after(block, new_inst); But blocks can consist of a single control flow instruction, so inst will actually be the exec_list's head sentinel. We shouldn't use it as if it were a regular instruction, but it is safe to insert something after it. This patch avoids assert-failing because an exec_list sentinel wasn't in the basic block's instruction list. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add device limits for tess threads & URB entriesChris Forbes2015-02-174-0/+48
| | | | | | | | This should cover all platforms prior to Skylake. Signed-off-by: Chris Forbes <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]> Acked-by: Ben Widawsky <[email protected]>
* i915c: Use the actual MIN instruction.Kenneth Graunke2015-02-171-15/+1
| | | | | | | | | | | | | Matt Turner noticed that the hardware has always had a MIN instruction, but the driver always used MAX+MOV for no apparent reason. This should cut an instruction, and a temporary, allowing more programs to run in hardware. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Add a function to disassemble an instruction from the 4 dwords.Kenneth Graunke2015-02-171-0/+12
| | | | | | | | | I used this a while back when debugging GPU hangs, and it seems like it could be useful, so I figured I'd add it so people can use it in the debugger. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Do Sandybridge workaround flushes before each primitive.Kenneth Graunke2015-02-1711-84/+20
| | | | | | | | | | | | | | | | | | | | | | | Sandybridge requires the post-sync non-zero workaround in a ton of places, and if you ever miss one, the GPU usually hangs. Currently, we try to track exactly when a workaround flush is necessary (via the brw->batch.need_workaround_flush flag). This is tricky to get right, and we've botched it several times in the past. This patch unconditionally performs the post-sync non-zero flush at the start of each primitive's state upload (including BLORP). We drop the needs_workaround_flush flag, and drop all the other callers, as the flush has already been performed. We have no data to indicate that simply flushing all the time will hurt performance, and it has the potential to help stability. v2: Add post-sync workaround to initial GPU state upload to be extra cautious (suggested by Chad Versace). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/vec4: Silence unused parameter warningsIan Romanick2015-02-173-7/+5
| | | | | | | | | | | | | brw_vec4_copy_propagation.cpp:243:59: warning: unused parameter 'reg' [-Wunused-parameter] int arg, struct copy_entry *entry, int reg) ^ brw_vec4_generator.cpp:869:57: warning: unused parameter 'inst' [-Wunused-parameter] vec4_generator::generate_unpack_flags(vec4_instruction *inst, ^ Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/simd8vs: Fix SIMD8 atomicsBen Widawsky2015-02-161-8/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The short version: we need to set bits in R0.7 which provide a mask to be used for PS kill samples/pixels. Since the VS has no such concept, we just need to set all 1. The longer version... Execution for SIMD8 atomics is defined as follows: SIMD8: The low 8 bits of the execution mask are ANDed with 8 bits of the Pixel/Sample Mask from the message header. For the typed messages, the Slot Group in the message descriptor selects either the low or high 8 bits. For the untyped messages, the low 8 bits are always selected. The resulting mask is used to determine which slots are read into the destination GRF register (for read), or which slots are written to the surface (for write). If the header is not present, only the low 8 bits of the execution mask are used. The message header for untyped messages is defined in R0.7 "This field contains the 16-bit pixel/sample mask to be used for SIMD16 and SIMD8 messages. All 16 bits are used for SIMD16 messages. For typed SIMD8 messages, Slot Group selects which 8 bits of this field are used. For untyped SIMD8 messages, the low 8 bits of this field are used." Furthermore, "The message header for the untyped messages only needs to be delivered for pixel shader threads, where the execution mask may indicate pixels/samples that are enabled only due to derivative (LOD) calculations, but the corresponding slot on the surface must not be accessed." We're not using a pixel shader here, but AFAICT, this mask is used for all stages. This leaves two options, Remove the header, or make the VS code emit the correct thing for the header. I believe one of the goals of using SIMD8 VS was to get as much code reuse as possible, and so I chose the latter. Since the VS has no such thing as kill instructions, the mask is derived simple as all 1's. v2: Add a comment to the code (stolen from Curro on the mailing list) Change the control flow style (Curro + Jason) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=87258 Cc: Kristian Høgsberg <[email protected]> Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Francisco Jerez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* meta: Fix saving the results of the current occlusion queryNeil Roberts2015-02-161-7/+10
| | | | | | | | | | | | | | | | | | | | | | | | When restoring the current state in _mesa_meta_end it was previously trying to copy the on-going sample count of the current occlusion query into the new query after restarting it so that the driver will continue adding to the previous value. This wouldn't work for two reasons. Firstly, the query might not be ready yet so the Result member will usually be zero. Secondly the saved query is stored as a pointer to the query object, not a copy of the struct, so it is actually restarting the exact same object. Copying the result value is just copying between identical addresses with no effect. The call to _mesa_BeginQuery will have always reset it back to zero. This patch fixes it by making it actually wait for the query object to be ready before grabbing the previous result. The downside of doing this is that it could introduce a stall but I think this situation is unlikely so it might not matter too much. A better solution might be to introduce a real suspend/resume mechanism to the driver interface. This could be implemented in the i965 driver by saving the depth count multiple times like it does in the i945 driver. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88248 Reviewed-by: Carl Worth <[email protected]> Cc: "10.5" <[email protected]>
* i965/vec4: Override destination register writemask in sampler message send.Francisco Jerez2015-02-161-0/+1
| | | | | | | | | | | | This line was removed by accident in commit 16b911257440afbd77a6eb762e28df62e3c19bc7 causing a regression in the ES3-CTS.gtf.GL3Tests.shadow.shadow_execution_vert Khronos conformance test. It's necessary because the swizzle_result() code below expects all four components of the vector to be valid. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89094 Tested-by: Lu Hua <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Fix a crash in the texture gradient lowering pass with cube samplersIago Toral Quiroga2015-02-161-1/+3
| | | | | | | We need to swizzle the rhs to match the number of components in the writemask, otherwise we'll hit an assertion in ir_assignment. Reviewed-by: Ian Romanick <[email protected]>
* i965/fs: Handle U/UW-type immediates in the generator.Matt Turner2015-02-151-0/+6
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* i965/fs: Handle W/UW-type immediates in dump_instructions().Matt Turner2015-02-151-0/+2
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* i965: Let dump_instructions() work before calculate_cfg().Matt Turner2015-02-152-13/+28
| | | | Reviewed-by: Ben Widawsky <[email protected]>
* i965/fs: Call calculate_cfg() before optimize().Matt Turner2015-02-151-2/+4
| | | | | | The CFG is fundamental to the FS IR, not merely a piece of optimization. Reviewed-by: Ben Widawsky <[email protected]>
* i965: Optimize multiplication by -1 into a negated MOV.Matt Turner2015-02-152-0/+14
| | | | | | | instructions in affected programs: 968 -> 942 (-2.69%) helped: 4 Reviewed-by: Ian Romanick <[email protected]>
* i965: Add an is_negative_one() method.Matt Turner2015-02-152-0/+17
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/vec4/vp: Use vec4_visitor::CMP.Matt Turner2015-02-151-2/+1
| | | | | | | | | | | | | | | | | ... instead of emit(BRW_OPCODE_CMP, ...). In commit 6b3a301f I changed vec4_visitor::CMP to set the destination's type to that of src0. In the following commit (2335153f) I removed an apparently now unnecessary work around for Gen8 that did the same thing. But there was a single place that emitted a CMP instruction without using the vec4_visitor::CMP function. Use it there. And change dst_null_d to dst_null_f for good measure, since ARB vp doesn't have integers. Cc: "10.5" <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89032 Reviewed-by: Kenneth Graunke <[email protected]>
* i965/nir: Don't support gl_FrontFacing as an input variableJason Ekstrand2015-02-141-3/+0
| | | | | Reviewed-by: Connor Abbott <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/nir: Add support for nir_intrinsic_load_front_faceJason Ekstrand2015-02-141-1/+3
| | | | Reviewed-by: Matt Turner <[email protected]>
* r200: Drop unused variable.Eric Anholt2015-02-121-1/+0
| | | | | | | | Quiets compiler warning since e7f2f2dea5acdbd1a12ed88914e64a38a97432f0. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* i965: Quiet another compiler warning about uninitialized values.Eric Anholt2015-02-121-2/+2
| | | | | | | | The compiler can't tell that we're always going to hit the first if block on the first time through the loop. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Move some asserts to unreachable.Eric Anholt2015-02-121-2/+2
| | | | | | | | | | If execution was supposed to be supported in this case, we'd run into trouble from completely uninitialized sat_imm values. v2: Drop the '!' before the string. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Shut up a compiler warning about uninitialized var.Eric Anholt2015-02-121-1/+1
| | | | | | | | We always pass this argument, even if it won't be used by the particular texture op. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/vs/skl: Use vec4 datatypes for message headerBen Widawsky2015-02-111-2/+2
| | | | | | | | | | | | | | | | | | | | | | | We're using a SIMD4x2 sampler message, which has execsize 4, and so the register width must be <= 4. Use <4,4,1> regioning instead of <8,8,1> regioning to access the same data but avoid tripping the assert. Fixes the following piglit tests: spec/glsl-1.20/compiler/structure-and-array-operations/array-selection.vert spec/glsl-es-3.00/compiler/uniform_block/interface-name-basic.vert spec/glsl-es-3.00/compiler/uniform_block/interface-name-field-clashes-with-struct.vert spec/glsl-es-3.00/compiler/uniform_block/interface-name-field-clashes-with-function.vert spec/glsl-es-3.00/compiler/uniform_block/interface-name-array.vert glslparsertest/glsl2/condition-07.vert spec/glsl-es-3.00/compiler/uniform_block/interface-name-field-clashes-with-variable.vert v2: Better commit message courtesy of Ken. I had a discussion with Ken, and we both question how we end up with a mov and execsize 4. For now though, this fixes the piglit tests, so we can worry about it later. Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add LINTERP/CINTERP to can_do_cmod().Matt Turner2015-02-111-0/+2
| | | | | | | | | | | | LINTERP is implemented as a PLN instruction or a LINE+MAC. PLN and MAC can do conditional mod. CINTERP is just a MOV. total instructions in shared programs: 5952103 -> 5950284 (-0.03%) instructions in affected programs: 324573 -> 322754 (-0.56%) helped: 1819 We lose the SIMD16 in one Unigine Heaven shader which appears six times in shader-db.
* i965/fs: Remove conditional mod when optimizing a SEL into a MOV.Matt Turner2015-02-111-0/+1
| | | | Missed in commit ca675b73, but got right in the companion commit 3c28b2c0.
* i965/vec4: Emit MADs from (x + abs(y * z)).Matt Turner2015-02-101-3/+15
| | | | | | | | | | Same as commit 3654b6d4 to the fs backend. total instructions in shared programs: 5945788 -> 5945787 (-0.00%) instructions in affected programs: 36 -> 35 (-2.78%) helped: 1 Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vec4: Emit MADs from (x + -(y * z)).Matt Turner2015-02-101-0/+12
| | | | | | | | | | | | | | Same as commit c4fab711 to the fs backend. total instructions in shared programs: 5945998 -> 5945788 (-0.00%) instructions in affected programs: 74665 -> 74455 (-0.28%) helped: 399 HURT: 180 It hurts some programs because we make no attempts in the vec4 backend to avoid MADs if they have constant (or vector uniform) arguments. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/skl: Implement WaDisable1DDepthStencilNeil Roberts2015-02-101-0/+12
| | | | | | | | | | | Skylake+ doesn't support setting a depth buffer to a 1D surface but it does allow pretending it's a 2D texture with a height of 1 instead. This fixes the GL_DEPTH_COMPONENT_* tests of the copyteximage piglit test (and also seems to avoid a subsequent GPU hang). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89037 Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen7-8: Implement glMemoryBarrier().Francisco Jerez2015-02-102-0/+41
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
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