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* i965: Simplify brw_get_renderer_string()Kenneth Graunke2020-01-131-20/+10
* i965: support EXT_EGL_image_storageGurchetan Singh2020-01-132-0/+30
* i965: refactor intel_image_target_texture_2dGurchetan Singh2020-01-131-4/+15
* i965: track if image is created by a dmabufGurchetan Singh2020-01-132-0/+2
* dri_util: add driImageFormatToSizedInternalGLFormat functionGurchetan Singh2020-01-132-45/+82
* mesa: create program resource hash in a single placeTapani Pälli2020-01-091-2/+0
* meta: Add cleanup function for BitmapYevhenii Kolesnikov2020-01-081-0/+17
* mesa/st/i965: add a ProgramResourceHash for quicker resource lookupTapani Pälli2020-01-071-0/+2
* glsl: rename gl_nir_link() to gl_nir_link_spirv()Timothy Arceri2020-01-071-1/+1
* i965: Allow HiZ for glCopyImageSubData sourcesJason Ekstrand2020-01-041-0/+9
* i965/blorp: Don't resolve HiZ unless we're reinterpretingJason Ekstrand2020-01-041-1/+1
* blorp: Allow reading with HiZJason Ekstrand2020-01-041-0/+6
* intel: Drop Gen11 WaBTPPrefetchDisable workaroundKenneth Graunke2020-01-031-13/+1
* meta: Cleanup function for DrawTexYevhenii Kolesnikov2019-12-301-0/+14
* meson: simplify install_megadrivers.py invocationEric Engestrom2019-12-271-2/+1
* i965/iris/perf: factor out frequency register captureLionel Landwerlin2019-12-181-22/+18
* i965: expose MESA_FORMAT_B8G8R8X8_SRGB visualTapani Pälli2019-12-171-7/+14
* dri: add __DRI_IMAGE_FORMAT_SXRGB8Tapani Pälli2019-12-171-0/+4
* i965/iris: perf-queries: don't invalidate/flush 3d pipelineLionel Landwerlin2019-12-131-1/+9
* st/glsl_to_nir: use nir based program resource list builderTimothy Arceri2019-12-131-2/+2
* glsl: move nir_remap_dual_slot_attributes() call out of glsl_to_nir()Timothy Arceri2019-12-131-0/+8
* i965: Enable GL_EXT_gpu_shader4 on Gen6+Jason Ekstrand2019-12-121-0/+1
* intel/decoder: Make get_state_size take a full 64-bit address and a baseKenneth Graunke2019-12-101-3/+4
* blorp: Pass the VB size to the VF cache workaroundJason Ekstrand2019-12-051-0/+1
* mesa: Silence unused parameter warningIan Romanick2019-12-046-10/+10
* i965: update Makefile.sources for perf changesJonathan Gray2019-11-291-2/+0
* driconf, glsl: Add a vs_position_always_invariant optionKenneth Graunke2019-11-271-0/+3
* i965: Ensure that all 2101010 image imports can pass framebuffer completeness.Miguel Casas-Sanchez2019-11-191-2/+6
* Call shmget() with permission 0600 instead of 0777Brian Paul2019-11-181-1/+2
* intel/compiler: Add a flag to avoid compacting push constantsJason Ekstrand2019-11-181-0/+1
* i965: Unify CC_STATE and BLEND_STATE atoms on Haswell as a workaroundDanylo Piliaiev2019-11-181-2/+35
* i965/program_cache: Lift restriction on shader key sizeDanylo Piliaiev2019-11-121-12/+4
* Meson: Remove lib prefix from graw and osmesa when building with Mingw.Prodea Alexandru-Liviu2019-11-071-0/+2
* mesa: Prepare for the MESA_FORMAT_* enum to be sparse.Eric Anholt2019-11-071-0/+2
* util: rename PIPE_ARCH_*_ENDIAN to UTIL_ARCH_*_ENDIANDylan Baker2019-11-057-14/+14
* util/u_endian: set PIPE_ARCH_*_ENDIAN to 1Dylan Baker2019-11-057-14/+14
* dri/osmesa: use preprocessor for selecting endian code pathsDylan Baker2019-11-051-6/+9
* r100: Use preprocessor to select big vs little endian pathsDylan Baker2019-11-053-46/+51
* r200: use preprocessor for big vs little endian checksDylan Baker2019-11-052-45/+38
* radeon: replace xmlpool_options_h with idep_xmlconfig_headersEric Engestrom2019-10-311-2/+2
* r200: replace xmlpool_options_h with idep_xmlconfig_headersEric Engestrom2019-10-311-2/+2
* nouveau: replace xmlpool_options_h with idep_xmlconfig_headersEric Engestrom2019-10-311-2/+2
* i915: replace xmlpool_options_h with idep_xmlconfig_headersEric Engestrom2019-10-311-2/+2
* dri: replace xmlpool_options_h with idep_xmlconfig_headersEric Engestrom2019-10-311-2/+2
* intel: Support HIZ_CCS in isl_surf_get_ccs_surfNanley Chery2019-10-282-8/+8
* i965/miptree: Avoid -Wswitch for the Gen12 aux modesNanley Chery2019-10-281-0/+3
* util: rename list_empty() to list_is_empty()Timothy Arceri2019-10-281-1/+1
* i965: setup sized internalformat for MESA_FORMAT_R10G10B10A2_UNORMTapani Pälli2019-10-281-1/+9
* intel/perf: move registers to their own headerLionel Landwerlin2019-10-232-1/+2
* mesa: Redefine the RG formats as array formats.Eric Anholt2019-10-203-10/+10
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