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* intel: Add missing includes for building on AndroidClayton Craft2018-03-061-0/+1
* intel: Drop SURFACE_FORMAT enum from genxml.Kenneth Graunke2018-03-051-4/+4
* intel: Split gen_device_info out into libintel_devJordan Justen2018-03-055-4/+6
* i965: Silence unused parameter warnings in genX_state_uploadIan Romanick2018-03-021-20/+14
* i965: Silence unused parameter warnings in blorpIan Romanick2018-03-022-10/+10
* i965: Silence unused parameter warnings in generated OA codeIan Romanick2018-03-021-1/+1
* i965: Silence unused parameter warningsIan Romanick2018-03-021-1/+1
* i965: Mark upload buffers with MAP_ASYNC and MAP_PERSISTENT.Kenneth Graunke2018-03-021-1/+3
* i965: Generalize intel_upload.c to support multiple uploaders.Kenneth Graunke2018-03-029-91/+101
* i965: Allow 48-bit addressing on Gen8+.Kenneth Graunke2018-03-017-18/+127
* i965: Shorten the name of the workaround BO.Kenneth Graunke2018-03-011-3/+1
* i965: Add debugging code to dump the validation list.Kenneth Graunke2018-03-011-0/+22
* i965: Fix RELOC_WRITE typo in brw_store_data_imm64()Andriy Khulap2018-03-011-1/+1
* i965/sbe: fix number of inputs for active componentsIago Toral Quiroga2018-03-011-4/+2
* Revert "i965: Only emit 3DSTATE_DRAWING_RECTANGLE once on gen8+"Mark Janes2018-02-283-13/+2
* i965: Only emit 3DSTATE_DRAWING_RECTANGLE once on gen8+Jason Ekstrand2018-02-283-2/+13
* i965: Be more clever about setting up our viewport clipJason Ekstrand2018-02-281-8/+12
* intel: Disable 64-bit extensions on platforms without 64-bit typesMatt Turner2018-02-281-4/+5
* i965: Warn about preliminary support for Gen11Matt Turner2018-02-281-0/+7
* i965: use context priority definitions from gen_defines.hTapani Pälli2018-02-283-10/+10
* i965: Use gen_get_pci_device_id_overrideJordan Justen2018-02-271-52/+5
* glsl: Specify framebuffer fetch coherency mode in lower_blend_equation_advanc...Francisco Jerez2018-02-241-1/+2
* mesa: Rename MESA_shader_framebuffer_fetch gl_extensions bits to EXT.Francisco Jerez2018-02-245-7/+7
* mesa: Rename dd_function_table::BlendBarrier to match latest EXT spec.Francisco Jerez2018-02-241-2/+2
* i965: Fix KHR_blend_equation_advanced with some render targets.Francisco Jerez2018-02-241-1/+3
* mesa: expose ARB_enhanced_layouts in the compatibility profileMarek Olšák2018-02-231-1/+2
* mesa: enable OpenGL 3.1 with ARB_compatibilityMarek Olšák2018-02-231-8/+0
* mesa: Add flush_vertices to _mesa_bind_vertex_buffer.Mathias Fröhlich2018-02-231-7/+9
* mesa: Add flush_vertices to _mesa_{enable,disable}_vertex_array_attrib.Mathias Fröhlich2018-02-231-7/+11
* mesa: Provide an alternative to get_vp_mode()Mathias Fröhlich2018-02-231-0/+2
* i965: perf: ensure reading config IDs from sysfs isn't interruptedLionel Landwerlin2018-02-231-1/+2
* i965: Use finish_external instead of make_shareable in setTexBuffer2Jason Ekstrand2018-02-215-2/+87
* i965/tex_image: Reference the renderbuffer miptree in setTexBuffer2Jason Ekstrand2018-02-211-14/+5
* i965/tex_image: Pull the tex format from the renderbuffer in intelSetTexBuffer2Jason Ekstrand2018-02-211-15/+19
* i965/miptree: Loosen the format check in miptree_match_imageJason Ekstrand2018-02-214-6/+8
* i965/state: Ignore intel_obj->_Format for depth/stencil and ETC2Jason Ekstrand2018-02-211-1/+15
* i965: Enable disk shader cache by defaultJordan Justen2018-02-201-3/+0
* mesa: add xbgr support adjacent to xrgbIlia Mirkin2018-02-191-0/+10
* i965: Use absolute addressing for constant buffer 0 on Kernel 4.16+.Kenneth Graunke2018-02-172-1/+32
* i965: Stop restoring the default L3 configuration on Kernel 4.16+.Kenneth Graunke2018-02-173-2/+7
* i965: Fix aux-surface size checkDaniel Stone2018-02-172-3/+12
* i965: Implement GenerateMipmap directly, rather than using Meta.Kenneth Graunke2018-02-165-0/+135
* i965/icl: Add render target flush after uploading binding tableAnuj Phogat2018-02-151-0/+14
* i965/icl: Enable float blend optimization and Wa3DStateModeAnuj Phogat2018-02-151-1/+1
* intel/common/icl: Add has_sample_with_hiz flag in gen_device_infoAnuj Phogat2018-02-151-4/+1
* i965/icl: Add assertions to check dispatch mode is SIMD8Anuj Phogat2018-02-151-0/+5
* i965/icl: Update switch statementsAnuj Phogat2018-02-152-0/+2
* i965/icl: Update the assert in brw_memory_barrier()Anuj Phogat2018-02-151-1/+1
* i965/icl: Define and use icl mocs settingsAnuj Phogat2018-02-153-1/+11
* i965/icl: Update the comment for maximum number of threads per PSDAnuj Phogat2018-02-151-4/+5
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