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| * r300: Renamed the CACHE_CTLSTAT values to include UNKNOWN in the name; notOliver McFadden2007-03-134-11/+11
| * Add defines for the values written to R300_RB3D_ZCACHE_CTLSTAT.Oliver McFadden2007-03-133-3/+5
| * Documented the value written for R300_TX_CNTL cache flush.Oliver McFadden2007-03-132-1/+3
| * Corrected values written to R300_RB3D_DSTCACHE_CTLSTAT to eitherOliver McFadden2007-03-133-4/+4
| * Guess another unknown register used for R300 pacification.Oliver McFadden2007-03-133-3/+7
| * i915tex: Don't crash when intel_fb->color_rb[i] is NULL.Michel Dänzer2007-03-121-1/+5
* | move CLIENT_ID code in xmesa_delete_framebuffer(), see bug 7205Brian2007-03-141-6/+3
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* r200: Simplify r200SetCliprects like radeonSetCliprects in radeon and r300.Alan Swanson2007-03-124-22/+22
* r200: Adapt cliprect fixes from r300.Alan Swanson2007-03-123-3/+6
* radeon: Adapt cliprect fixes from r300.Alan Swanson2007-03-123-5/+8
* fix for bug#10196Xiang, Haihao2007-03-111-1/+8
* Guess another unknown register in R300 command buffer initialization. (Oliver...Aapo Tahkola2007-03-114-5/+6
* Renamed some of the unkXXX variables in the command buffer initOliver McFadden2007-03-113-72/+73
* i915tex: Fix build against libdrm git...Michel Dänzer2007-03-102-2/+3
* i915tex: Fix intel_wait_flips being declared implicitly.Michel Dänzer2007-03-101-0/+1
* i915tex: Fix build against released version of libdrm.Michel Dänzer2007-03-101-0/+17
* nouveau: fix nv04 swtcl.Stephane Marchesin2007-03-101-0/+1
* nouveau: fix the nv04 swtcl code.Stephane Marchesin2007-03-101-1/+1
* nouveau: oops don't debug by default.Stephane Marchesin2007-03-101-1/+1
* nouveau: some fixes to the nv04 state code.Stephane Marchesin2007-03-101-13/+15
* nouveau: add a fifo size debug check.Stephane Marchesin2007-03-102-3/+23
* Merge branch 'i915tex-pageflip'Michel Dänzer2007-03-1012-304/+608
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| * i915tex: Wait for pending scheduled flips before switching vsync pipe.Michel Dänzer2007-03-091-0/+19
| * i915tex: Set intel_fb->vbl_waited to current instead of what we aimed for.Michel Dänzer2007-03-091-1/+1
| * i915tex: Sync pages between pipes immediately again.Michel Dänzer2007-03-091-2/+12
| * i915tex: Do not wait for pending flips on both pipes at the same time.Michel Dänzer2007-03-091-9/+4
| * i915tex: Set framebuffer size to match window before calling _mesa_make_current.Michel Dänzer2007-03-071-10/+10
| * i915tex: Sync pages differently when crossing pipe borders.Michel Dänzer2007-02-281-12/+18
| * i915tex: Check that intel_rb is valid before trying to add it to an fbo.Michel Dänzer2007-02-281-2/+4
| * i915tex: Also update intel_rb->vbl_pending when scheduled swap is not a flip.Michel Dänzer2007-02-281-3/+3
| * i915tex: Schedule flips when possible.Michel Dänzer2007-02-226-179/+228
| * i915tex: Triple buffering support, only effective with page flipping so far.Michel Dänzer2007-02-207-63/+166
| * intelWindowMoved: Some debugging output was accidentally left always enabled.Michel Dänzer2007-02-201-1/+1
| * intelRotateWindow: Only use back buffer and cliprects in very specific cases.Michel Dänzer2007-02-201-7/+6
| * intelCopyBuffer: Remove incorrect intel_fb->pf_current_page tests.Michel Dänzer2007-02-201-17/+4
| * i915tex: Support page flipping on both CRTCs independently.Michel Dänzer2007-02-2010-117/+203
| * i915tex: Make page flipping work again.Michel Dänzer2007-02-207-46/+94
* | r300: Also update window state when it's already bound but its stamp changed.Michel Dänzer2007-03-091-4/+4
* | i945_miptree_layout: Adapt cubemap fixes from i915_miptree_layout.Michel Dänzer2007-03-071-3/+8
* | fix renderbuffer mem leakBrian2007-03-061-0/+12
* | formatting fixBrian2007-03-061-4/+2
* | Fix/improve framebuffer object reference counting.Brian2007-03-0623-33/+25
* | r300: Call radeonSetCliprects from radeonMakeCurrent.Michel Dänzer2007-03-063-1/+5
* | fix for bug#10182Xiang, Haihao2007-03-064-4/+8
* | fix for bug#9971Xiang, Haihao2007-03-051-0/+1
* | r300: Use register name & add a register about shading.Christoph Bill2007-03-012-9/+13
* | r300: Use reg definition when available & add missing reg definition.Christoph Bill2007-03-013-3/+9
* | Add early register descritpion.Christoph Bill2007-03-012-7/+11
* | Optimize cos&sin instruction a bit more.Rune Petersen2007-03-011-168/+146
* | Merge branch 'master' of git+ssh://[email protected]/git/mesa/mesaBrian2007-02-286-38/+64
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