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* i965: Gut the separate OpenGL ES extension enabling.Kenneth Graunke2012-05-237-148/+4
| | | | | | | | | | | | | | | | | | | | | | | | We should just set the bits of functionality that we support; the GL/ES1/ES2 flags in extensions.c will take care of advertising the appropriate extensions for the current API. This enables the GL_EXT_texture_compression_dxt1 extension on ES1/ES2 when libtxc_dxtn is installed or the force_s3tc driconf option is set. The main extension code set this up properly, but the ES-specific code failed to do so. Otherwise, the extension strings reported by es1_info, es2_info, and glxinfo all remain the same. This patch manually disables the ARB_framebuffer_object bit on ES to preserve the behavior of 1c0f5d8324c4db2720247989ddc4a45315b55a85. v2: Rebase, fix the i915 Makefile, and unconditionally set the OES_draw_texture bit as core Mesa will only apply it to ES1 now. Tested-by: Daniel Charles <[email protected]> [v1] Reviewed-by: Chad Versace <[email protected]> [v1] Signed-off-by: Kenneth Graunke <[email protected]>
* i965: use cut index to handle primitive restart when possibleJordan Justen2012-05-231-1/+80
| | | | | | | | | | | | | If the primitive restart index and the primitive type can be handled by the cut index feature, then use the hardware to handle the primitive restart feature. The VBO module's software handling of primitive restart is used as a fall back. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: add flag to enable cut_indexJordan Justen2012-05-234-1/+12
| | | | | | | | | When brw->prim_restart.enable_cut_index is set, the cut index will be enabled when uploading index_buffer commands. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: create code path to handle primitive restart in hardwareJordan Justen2012-05-237-0/+112
| | | | | | | | | | | | | | For newer hardware we disable the VBO module's software handling of primitive restart. We now handle primitive restarts in brw_handle_primitive_restart. The initial version of brw_handle_primitive_restart simply calls vbo_sw_primitive_restart, and therefore still uses the VBO module software primitive restart support. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/gen6+: Add support for GL_ARB_blend_func_extended.Eric Anholt2012-05-2313-8/+112
| | | | | | | v2: Add support for gen6, and don't turn it on if blending is disabled. (fixes GPU hang), and note it in docs/GL3.txt Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen6+: Add support for fast depth clears.Eric Anholt2012-05-238-12/+150
| | | | | | | | | | Improves citybench high-res performance 3.0% +- 0.4%, n=10. Improves Lightsmark 1024x768 performance 0.74% +/- 0.20% (n=78). No significant difference on openarena (n=5, didn't fast clear) or nexuiz (n=3). Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/gen6: Add CC viewport state setup to blorp code.Eric Anholt2012-05-231-0/+26
| | | | | | | | While it doesn't have the same warning in the simulator as in gen7, let's emit it out of paranoia. We wouldn't want our resolves of some previous clear to get clamped to some current clamping value. Suggested-by: pretty much everyone
* i965/gen7: Add CC viewport setup to blorp code.Eric Anholt2012-05-231-0/+21
| | | | | | | | | | | | | | | When doing fast clears, a fulsim warning said that the batch was being emitted without the viewport set up. While the fast clear pass I was looking at doesn't use the clear value, the later resolves which also didn't set up the vieport would trigger the same. It's not obvious from the error message whether it meant "fast clear value gets clamped to something you haven't defined" or "fast clear value doesn't get clamped, and I saw it was out of the current (uninitialized) range, and you probably wanted it clamped to that (uninitialized) range". Be paranoid and assume the first case. Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Drop a layer of indirection in doing HiZ resolves.Eric Anholt2012-05-237-120/+9
| | | | | Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Replace intel_need_resolve with the hiz ops it maps to.Eric Anholt2012-05-233-17/+21
| | | | | | | | Having this enum separate caused us to need a bunch of helper functions to translate to the op to be executed. Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Add an interface for doing hiz ops from C code.Eric Anholt2012-05-234-15/+44
| | | | | | | | This required moving gen6_hiz_op, and I put it in intel_resolve_map.h for the next commit. Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Rename the clear function for this driver.Eric Anholt2012-05-231-2/+2
| | | | | Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Simplify the remaining clear logic by relying on the meta clear.Eric Anholt2012-05-231-47/+11
| | | | | | | | The GLSL clear path doesn't need any buffer presence checks, since those are already handled in the normal drawing path code. Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Switch blit color clears to tri clears on gen4/5.Eric Anholt2012-05-231-28/+2
| | | | | | | | | | | | | | Our understanding is that the 3D engine is supposed to be faster anyway. We used to have more overhead in our tri clear path than we do today, which would have led to this choice. But given that we almost always see a depth clear along with a color clear, the path was hardly exercised anyway. Also, the color mask logic was broken in the presence of GL_EXT_draw_buffers2's per-buffer colormask. Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Remove dead logic for non-tri depth/stencil clears.Eric Anholt2012-05-231-26/+2
| | | | | Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: We always have GLSL, so always use it for tri clears.Eric Anholt2012-05-231-4/+1
| | | | | Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i915: Drop gen4+ code from the forked clear code.Eric Anholt2012-05-231-10/+1
| | | | | Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* intel: Fork the intel_clear.c file between i915 and i965.Eric Anholt2012-05-234-8/+209
| | | | | | | | This logic is wasted on i965 when we want to just always do GLSL tri clears. Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Completely annotate the batch bo when aub dumping.Paul Berry2012-05-226-27/+117
| | | | | | | | | | | | | | | | | | | Previously, when the environment variable INTEL_DEBUG=aub was set, mesa would simply instruct DRM to start dumping data to an .aub file, but we would not provide DRM with any information about the format of the data in various buffers. As a result, a lot of the data in the generate .aub file would be unannotated, making further data analysis difficult. This patch causes the entire contents of each batch buffer to be annotated using the data in brw->state_batch_list (which was previously used only to annotate the output of INTEL_DEBUG=bat). This includes data that was allocated by brw_state_batch, such as binding tables, surface and sampler states, depth/stencil state, and so on. The new annotation mechanism requires DRM version 2.4.34. Reviewed-by: Eric Anholt <[email protected]>
* intel: When AUB dumping, flush before emitting final bitmap command.Paul Berry2012-05-221-1/+3
| | | | | | | | | | | | | When we are generating an AUB dump, we make a final call to aub_dump_bmp() as the context is being destroyed, to ensure that any rendering performed before the application exits can be seen during a simulation run. However, we were doing this before flushing the batch buffer; as a result simulation runs would not always see the effect of all rendering commands. This patch flushes the batch buffer just before making the final call to aub_dump_bmp(), to ensure that all rendering is properly captured in the final bitmap.
* i965/vs: Fix up swizzle for dereference_array of matrices.Eric Anholt2012-05-171-2/+2
| | | | | | | | | Fixes assertion failure in piglit: vs-mat2-struct-assignment.shader_test vs-mat2-array-assignment.shader_test Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/fs: Do more register coalescing by using the interference graph.Eric Anholt2012-05-172-0/+62
| | | | | | | | | | | | | | By using the live variables code for determining interference, we can handle coalescing in the presence of control flow, which the other register coalescing path couldn't. Total instructions: 207184 -> 206990 74/1246 programs affected (5.9%) 33993 -> 33799 instructions in affected programs (0.6% reduction) There is a newerth shader that loses out, because of some extra MOVs that now get their dead-code nature obscured by coalescing. This should be fixed by doing better at dead code elimination.
* i965/blorp: Move exec() out of brw_blorp_params.Paul Berry2012-05-153-6/+9
| | | | | | | | | No functional change. This patch replaces the brw_blorp_params::exec() method with a global function brw_blorp_exec() that performs the operation described by the params data structure. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen6: Initial implementation of MSAA.Paul Berry2012-05-1523-121/+662
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables MSAA for Gen6, by modifying intel_mipmap_tree to understand multisampled buffers, adapting the rendering pipeline setup to enable multisampled rendering, and adding multisample resolve operations to brw_blorp_blit.cpp. Some preparation work is also included for Gen7, but it is not yet enabled. MSAA support is still fairly preliminary. In particular, the following are not yet supported: - Fully general blits between MSAA and non-MSAA buffers. - Formats other than RGBA8, DEPTH24, and STENCIL8. - Centroid interpolation. - Coverage parameters (glSampleCoverage, GL_SAMPLE_ALPHA_TO_COVERAGE, GL_SAMPLE_ALPHA_TO_ONE, GL_SAMPLE_COVERAGE, GL_SAMPLE_COVERAGE_VALUE, GL_SAMPLE_COVERAGE_INVERT). Fixes piglit tests "EXT_framebuffer_multisample/accuracy" on i965/Gen6. v2: - In intel_alloc_renderbuffer_storage(), quantize the requested number of samples to the next higher sample count supported by the hardware. This ensures that a query of GL_SAMPLES will return the correct value. It also ensures that MSAA is fully disabled on Gen7 for now (since Gen7 MSAA support doesn't work yet). - When reading from a non-MSAA surface, ensure that s_is_zero is true so that we won't try to read from a nonexistent sample.
* i965/gen6+: Add code to perform blits on the render path ("blorp").Paul Berry2012-05-158-27/+1730
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch expands the "blorp" component to be able to perform blits as well as HiZ resolves. The new blitting code is located in brw_blorp_blit.cpp. This includes the necessary fragment shader code to look up pixels in the source buffer (which is configured as a texture) and output them to the destination buffer (which is configured as the render target). Most of the time the fragment shader code is simple and straightforward, since it merely has to apply a coordinate offset, read from the texture, and write to the render target. However, in the case of blitting stencil buffers, things are more complicated, since the GPU stores stencil data using W tiling, and W tiling is not supported for textures or render targets. So, we set up the stencil buffers as Y tiled, and emit fragment shader code that adjusts the coordinates to account for the difference between W and Y tiling. Furthermore, since a rectangular region in W tiling does not necessarily correspond to a rectangular region in Y tiling, we widen the rectangle primitive to the nearest tile boundary and have the fragment shader "kill" any pixels that don't fall inside the actual desired destination rectangle. All of this is a necessary prerequisite for implementing MSAA, since we'll need to be able to blit between multisample color, depth, and stencil buffers and their non-multisampled counterparts, and none of the existing blitting mechanisms support multisampling. In addition, the new blitting code should speed up operations where we previously fell back to software rasterization, such as blitting of stencil buffers. The current fallback sequence is: first we try to do a blit using the hardware blitting engine. If that fails we try to do a blit using the render path. If that also fails then we do the blit using a meta-op (which may or may not fall back to software rasterization). Note that blitting using the render path has some limitations at the moment: it only supports a few formats, and it doesn't support clipping or scissoring. These limitations will be addressed in future patch series. v2: - Add the code that configures the WM program to gen{6,7}_emit_wm_config() and gen7_emit_ps_config() rather than creating separate ...enable() functions. - Call intel_prepare_render before determining which miptrees we are blitting from/to, because it may cause miptrees to be reallocated. - Allow the blit to mirror X and/or Y coordinates. - Disable blorp blits on Gen7 for now, since they aren't working yet.
* i965: Expose surface setup internals for use by blits.Paul Berry2012-05-153-2/+4
| | | | | | | | This patch exposes the functions brw_get_surface_tiling_bits and gen7_set_surface_tiling, so that they can be re-used when setting up surface states in gen6_blorp.cpp and gen7_blorp.cpp. Reviewed-by: Chad Versace <[email protected]>
* i965: split gen{6,7}_blorp_exec functions into manageable chunks.Paul Berry2012-05-153-522/+647
| | | | | | | | | | | | | | | | | This patch splits up the gen6_blorp_exec and gen7_blorp_exec functions, which were very long, into simple component functions. With a few exceptions, there is one function per state packet. This will allow blit functionality to be added without significantly complicating the code. Reviewed-by: Chad Versace <[email protected]> v2: Rename the functions gen{6,7}_emit_wm_disable() to gen{6,7}_emit_wm_config() (since the WM is not actually disabled during HiZ ops; it simply doesn't have a program). Also, on gen7, split out the configration of 3DSTATE_PS to a separate function gen7_emit_ps_config().
* i965: Parameterize HiZ code to prepare for adding blitting.Paul Berry2012-05-157-177/+335
| | | | | | | | | | | | | | | | | | | This patch groups together the parameters used by the HiZ functions into a new data structure, brw_hiz_resolve_params, rather than passing each parameter individually between the HiZ functions. This data structure is a subclass of brw_blorp_params, which represents the parameters of a general-purpose blit or resolve operation. A future patch will add another subclass for blits. In addition, this patch generalizes the (width, height) parameters to a full rect (x0, y0, x1, y1), since blitting operations will need to be able to operate on arbitrary rectangles. Also, it renames several of the HiZ functions to reflect the expanded role they will serve. v2: Rename brw_hiz_resolve_params to brw_hiz_op_params. Move gen{6,7}_blorp_exec() functions back into gen{6,7}_blorp.h. Reviewed-by: Chad Versace <[email protected]>
* i965: Implement guardband clipping on Ivybridge.Kenneth Graunke2012-05-152-5/+15
| | | | | | | | | | | Improves performance in Citybench: - 320x240: 9.19589% +/- 0.557621% - 1280x480: 3.90797% +/- 0.774429% No apparent difference in OpenArena. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Implement guardband clipping on Sandybridge.Kenneth Graunke2012-05-152-10/+15
| | | | | | | | | | | Improves performance in Citybench: - 320x240: 19.8008% +/- 0.937818% - 1280x480: 6.53856% +/- 0.859083% No apparent difference in OpenArena nor Xonotic. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* Revert "i965/fs: Jump from discard statements to the end of the program when ↵Eric Anholt2012-05-144-126/+5
| | | | | | | | | | done." This reverts commit 31866308fcf989df992ace28b5b986c3d3770e90. Fixes piglit glsl-fs-discard-exit-3 and unigine tropics rendering. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Remove the requirement of no dead code for interference checks.Eric Anholt2012-05-141-12/+12
| | | | | | | | This will be convenient when I want to comment out optimization code to see the raw program being optimized, but more importantly will let the interference check be used during optimization. Acked-by: Kenneth Graunke <[email protected]>
* i965/fs: Add support for copy propagation.Eric Anholt2012-05-145-0/+143
| | | | | | | | | | | | We could do more by handling abs/negate and non-GRF sources, but this is a good start. Improves tropics performance 0.30% +/- .17% (n=43). shader-db results: Total instructions: 208032 -> 207184 60/1246 programs affected (4.8%) 23286 -> 22438 instructions in affected programs (3.6% reduction) Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: When doing no work for live interval calculation, do no allocation.Eric Anholt2012-05-141-7/+7
| | | | | | | | | When I had a bug causing the backend to never finish optimizing, it also sent me deep into swap. This avoids extra memory allocation per trip through optimization, and thus may reduce the peak memory allocation of the driver even in the success case. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen7: Set tile_x/y to 0 in the no-stencil case.Eric Anholt2012-05-141-1/+1
| | | | Fixes compiler warnings.
* intel: Fix signed/unsigned comparison warnings.Eric Anholt2012-05-142-5/+6
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* intel: Fix compile warning from 7b6424143d8bf572cadd46adcbaa91d2a5598635Eric Anholt2012-05-141-2/+2
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* intel: Fix compiler warning from 3cd7bee48f7caf7850ea64d40f43875d4c975507Eric Anholt2012-05-141-2/+0
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* i965/fs: Add a local common subexpression elimination pass.Kenneth Graunke2012-05-144-0/+201
| | | | | | | | | | | | | | | | | Total instructions: 18210 -> 17836 49/163 programs affected (30.1%) 12888 -> 12514 instructions in affected programs (2.9% reduction) This reduces Lightsmark's "Scale down filter" shader from 395 instructions to 283, a whopping 28%. It also reduces register pressure significantly: the SIMD8 program now uses 29 registers instead of 101, giving us more than enough room for a SIMD16 program. v2: Add && !inst->conditional_mod to the "skip some instructions" check. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965/fs: Use a const reference in fs_reg::equals instead of a pointer.Kenneth Graunke2012-05-143-16/+16
| | | | | | | | | | This lets you omit some ampersands and is more idiomatic C++. Using const also marks the function as not altering either register (which was obvious, but nice to enforce). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* nouveau/vieux: finish != flush, how about we do that..Ben Skeggs2012-05-123-0/+23
| | | | Signed-off-by: Ben Skeggs <[email protected]>
* i965/hiz: Convert gen{6,7}_hiz.h to gen{6,7}_blorp.hPaul Berry2012-05-105-5/+5
| | | | | | | This patch renames the gen6_hiz.h and gen7_hiz.h files to correspond to the renames of the corresponding .cpp files (see previous commit). Reviewed-by: Chad Versace <[email protected]>
* i965/hiz: Convert gen{6,7}_hiz.c to C++Paul Berry2012-05-103-3/+3
| | | | | | | | | | | This patch converts the files gen6_hiz.c and gen7_hiz.c to C++, in preparation for expanding the HiZ code to support arbitrary blits. The new files are called gen6_blorp.cpp and gen7_blorp.cpp to reflect the expanded role that this code will serve--"blorp" stands for "BLit Or Resolve Pass". Reviewed-by: Chad Versace <[email protected]>
* i965/hiz: Make void pointer type casts explicitPaul Berry2012-05-101-5/+7
| | | | | | | | | Previous to this patch, gen6_hiz.c contained two implicit type casts from void * to a a non-void pointer type. This is allowed in C but not in C++. This patch makes the type casts explicit, so that gen6_hiz.c can be converted into a C++ file. Reviewed-by: Chad Versace <[email protected]>
* intel: Work around differences between C and C++ scoping rules.Paul Berry2012-05-102-25/+29
| | | | | | | | | | | | | | In C++, if a struct is defined inside another struct, or its name is first seen inside a struct or function, the struct is nested inside the namespace of the struct or function it appears in. In C, all structs are visible from toplevel. This patch explicitly moves the decalartions of intel_batchbuffer to toplevel, so that it does not get nested inside a namespace when header files are included from C++. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* intel: Add extern "C" declarations to headersPaul Berry2012-05-1010-1/+75
| | | | | | | | These declarations are necessary to allow C++ code to call C code without causing unresolved symbols (which would make the driver fail to load). Reviewed-by: Chad Versace <[email protected]>
* i965: fix wrong cube/3D texture layoutYuanhan Liu2012-05-091-2/+3
| | | | | | | | | | | | | | | | | | | | | | Fix wrong cube/3D texture layout for the tailing levels whose width or height is smaller than the align unit. From 965 B-spec http://intellinuxgraphics.org/VOL_1_graphics_core.pdf at page 135: All of the LOD=0 q-planes are stacked vertically, then below that, the LOD=1 qplanes are stacked two-wide, then the LOD=2 qplanes are stacked four-wide below that, and so on. Thus we should always inrease pack_x_nr, which results to the pitch of LODn may greater than the pitch of LOD0. So we should refactor mt->total_width when needed. This would fix the following webgl test case on all gen4 platforms: conformance/textures/texture-size-cube-maps.html NOTE: This is a candidate for stable release branches. Signed-off-by: Yuanhan Liu <[email protected]>
* mesa: move gl_client_array*[] from vbo_draw_func into gl_contextMarek Olšák2012-05-083-7/+5
| | | | | | | | | | | | | | | | | | In the future we'd like to treat vertex arrays as a state and not as a parameter to the draw function. This is the first step towards that goal. Part of the goal is to avoid array re-validation for every draw call. This commit adds: const struct gl_client_array **gl_context::Array::_DrawArrays. The pointer is changed in: * vbo_draw_method * vbo_rebase_prims - unused by gallium * vbo_split_prims - unused by gallium * st_RasterPos Reviewed-by: Brian Paul <[email protected]>
* i965/Gen7: Work around GPU hangs due to misaligned depth coordinate offsets.Paul Berry2012-05-072-0/+54
| | | | | | | | | | | | | | | | | | | | In i965 Gen7, Mesa has for a long time used the "depth coordinate offset X/Y" settings (in 3DSTATE_DEPTH_BUFFER) to cause the GPU to render to miplevels other than 0. Unfortunately, this doesn't work, because these offsets must be aligned to multiples of 8, and miplevels in the depth buffer are only guaranteed to be aligned to multiples of 4. When the offsets aren't aligned to a multiple of 8, the GPU sometimes hangs. As a temporary measure, to avoid GPU hangs, this patch smashes the 3 LSB's of "depth coordinate offset X/Y" to 0. This results in incorrect rendering to mipmapped depth textures, but that seems like a reasonable stopgap while we figure out a better solution. Avoids GPU hangs in piglit test "depthstencil-render-miplevels" at texture sizes that are not powers of 2. Reviewed-by: Chad Verace <[email protected]>
* i965/Gen6: Work around GPU hangs due to misaligned depth coordinate offsets.Paul Berry2012-05-072-0/+54
| | | | | | | | | | | | | | | | | | | | | | | In i965 Gen6, Mesa has for a long time used the "depth coordinate offset X/Y" settings (in 3DSTATE_DEPTH_BUFFER) to cause the GPU to render to miplevels other than 0. Unfortunately, this doesn't work, because these offsets must be aligned to multiples of 8, and miplevels in the depth buffer are only guaranteed to be aligned to multiples of 4. When the offsets aren't aligned to a multiple of 8, the GPU sometimes hangs. As a temporary measure, to avoid GPU hangs, this patch smashes the 3 LSB's of "depth coordinate offset X/Y" to 0. This results in incorrect rendering to mipmapped depth textures, but that seems like a reasonable stopgap while we figure out a better solution. (Note that we have only ever observed this GPU hang on Gen6 when HiZ is enabled, so another possible stopgap would be to disable HiZ). Avoids GPU hangs in piglit test "depthstencil-render-miplevels" at texture sizes that are not powers of 2. Reviewed-by: Chad Verace <[email protected]>
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