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* i965: Print access flags in INTEL_DEBUG=buf output.Kenneth Graunke2017-07-011-3/+22
| | | | | | | | | | | | | | | | | Being able to see the access mode of various mappings is incredibly useful for debugging. With this patch, INTEL_DEBUG=buf now shows data such as: bo_create: buf 7 (bufferobj) 640b bo_map_gtt: 7 (bufferobj) -> 0x7fca1fae5000, WRITE ASYNC brw_bo_map_cpu: 7 (bufferobj) -> 0x7fca1fae4000, READ bo_map_gtt: 5 (bufferobj) -> 0x7fca1fad4000, WRITE ASYNC brw_bo_map_cpu: 7 (bufferobj) -> 0x7fca1fae4000, READ which makes it easy to see that there are async GTT writes with intervening CPU reads. Reviewed-by: Matt Turner <[email protected]>
* i965: Remove clearing of bo->map_gtt after failureChris Wilson2017-07-011-1/+0
| | | | | | | | | | | | With the conversion to storing the result of drm_mmap to a local and not directly to bo->map_gtt itself, we no longer should clear bo->map_gtt. In the best the operation is redundant as we know bo->map_gtt to already be NULL, but in the worst case we overwrite a concurrent thread that successfully mmaped the GTT. Fixes: 314647c4c206 ("i965: Drop global bufmgr lock from brw_bo_map_* functions.") Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add inline to brw_bo_unmapKenneth Graunke2017-06-301-1/+1
| | | | | I meant to do this in "i965: Make brw_bo_unmap a static inline." but botched the commit fixup.
* i965: Drop global bufmgr lock from brw_bo_map_* functions.Chris Wilson2017-06-301-14/+15
| | | | | | | | | | | | After removing the unusuable debugging code in the previous commit, we can also entirely remove the global mutex around mapping the buffer for the first time and replace it with a single atomic operation to update the cache once we retrieve the mmap. v2 (Ken): Split out from Chris's original commit. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Make brw_bo_unmap a static inline.Kenneth Graunke2017-06-302-7/+1
| | | | | | | | | | | With the broken debugging code gone, it doesn't do anything anymore. We could technically eliminate it, but I'd like to keep it around in case we want to add something there again someday. Otherwise we'd have to go all over the codebase adding unmap calls back again. Based on a patch by Chris Wilson. Reviewed-by: Matt Turner <[email protected]>
* i965: Discard bo->map_countChris Wilson2017-06-302-53/+3
| | | | | | | | | | | | | | | Supposedly we were keeping a reference count for the number of users of a mapping so that we could use valgrind to detect access to the map outside of the valid section. However, we were incrementing the counter only when first creating the cached mapping but decrementing on every unmap. The bo->map_count tracking was wrong and so the debugging code was completely useless. v2 (Ken): Separate out atomic compare and swap optimization. Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Add a comment about not needing VALGRIND_MALLOCLIKE_BLOCK.Kenneth Graunke2017-06-301-1/+3
| | | | | | | | | At first glance this seems missing, since we handle it manually for CPU and WC maps. Although a bit inconsistent, it's actually not necessary. Thanks to Chris Wilson for explaining this to me. Reviewed-by: Matt Turner <[email protected]>
* i965/i915: Add UYVY as the supported formatJohnson Lin2017-06-303-18/+31
| | | | | | Trigger the correct sampler options for it. Similar with YUYV Reviewed-by: Kristian H. Kristensen <[email protected]>
* Android: i965: remove libdrm_intel dependencyRob Herring2017-06-291-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | Commit 7dd20bc3ee8f ("anv/i965: drop libdrm_intel dependency completely") removed the libdrm_intel dependency for automake, but Android builds still depended on it. Now the build requires a newer version of i915_drm.h and fails on Android builds: src/mesa/drivers/dri/i965/brw_performance_query.c:616:9: error: use of undeclared identifier 'I915_OA_FORMAT_A32u40_A4u32_B8_C8' case I915_OA_FORMAT_A32u40_A4u32_B8_C8: ^ src/mesa/drivers/dri/i965/brw_performance_query.c:1887:18: error: use of undeclared identifier 'I915_PARAM_SLICE_MASK' gp.param = I915_PARAM_SLICE_MASK; ^ src/mesa/drivers/dri/i965/brw_performance_query.c:1893:18: error: use of undeclared identifier 'I915_PARAM_SUBSLICE_MASK' gp.param = I915_PARAM_SUBSLICE_MASK; ^ Remove the libdrm_intel dependency for Android builds and add the necessary include paths for the local copy of i915_drm.h. Fixes: 7dd20bc ("anv/i965: drop libdrm_intel dependency completely") Signed-off-by: Rob Herring <[email protected]> Reviewed-by: Juan A. Suarez Romero <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965: Drop index buffer re-alignment code.Kenneth Graunke2017-06-281-30/+8
| | | | | | | | | | | | | | | | This shouldn't ever happen - GL requires it to be aligned: "Clients must align data elements consistent with the requirements of the client platform, with an additional base-level requirement that an offset within a buffer to a datum comprising N basic machine units be a multiple of N." Mesa should reject unaligned index buffers for us - we shouldn't have to handle them in the driver. Note that Gallium already makes this assumption. Reviewed-by: Ian Romanick <[email protected]>
* i965: Fix anisotropic filtering for mag filterEero Tamminen2017-06-281-1/+1
| | | | | | | | | | | | | | Commit f8d69beed49c64f883bb8ffb28d4960306baf575 moving sampler handling to genxml messed up change done by commit 6a7c5257cac23cd9767aa4bc8fdab68925b11157. This broke rendering in SynMark CSDof and TexFilterAniso tests. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101607 Thanks to Kevin, who spotted the actual typo! Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/dri: Support R8G8B8A8 and R8G8B8X8 configsChad Versace2017-06-282-3/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Android framework requires support for EGLConfigs with HAL_PIXEL_FORMAT_RGBX_8888 and HAL_PIXEL_FORMAT_RGBA_8888. Even though all RGBX formats are disabled on gen9 by brw_surface_formats.c, the new configs work correctly on Broxton thanks to _mesa_format_fallback_rgbx_to_rgba(). On GLX, this creates no new configs, and therefore breaks no existing apps. See in-patch comments for explanation. I tested with glxinfo and glxgears on Skylake. On Wayland, this also creates no new configs, and therfore breaks no existing apps. (I tested with mesa-demos' eglinfo and es2gears_wayland on Skylake). The reason differs from GLX, though. In dri2_wl_add_configs_for_visual(), the format table contains only B8G8R8X8, B8G8R8A8, and B5G6B5; and dri2_add_config() correctly matches EGLConfig to format by inspecting channel masks. On Android, in Chrome OS, I tested this on a Broxton device. I confirmed that the Google Play Store's EGLSurface used HAL_PIXEL_FORMAT_RGBA_8888, and that an Asteroid game's EGLSurface used HAL_PIXEL_FORMAT_RGBX_8888. Both apps worked well. (Disclaimer: I didn't test this patch on Android with Mesa master. I backported this patch series to an older Android branch). Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965: Add a RGBX->RGBA fallback for glEGLImageTextureTarget2D()Chad Versace2017-06-271-2/+16
| | | | | | | | | | | | | | This enables support for importing RGBX8888 EGLImage textures on Skylake. Chrome OS needs support for RGBX8888 EGLImage textures because because the Android framework produces HAL_PIXEL_FORMAT_RGBX8888 winsys surfaces, which the Chrome OS compositor consumes as dma_bufs. On hardware for which RGBX is unsupported or disabled, normally core Mesa provides the RGBX->RGBA fallback during glTexStorage. But the DRIimage code bypasses core Mesa, so we must do the fallback in i965. Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: add missing includeEric Engestrom2017-06-271-0/+1
| | | | | | | | | | | src/mesa/drivers/x11/xm_dd.c:688:7: warning: implicit declaration of function ‘_mesa_update_draw_buffer_bounds’; did you mean ‘_mesa_has_ARB_draw_buffers_blend’? [-Wimplicit-function-declaration] _mesa_update_draw_buffer_bounds(ctx, ctx->DrawBuffer); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Cc: Marek Olšák <[email protected]> Fixes: 585c5cf8a514783d9ed3 ("mesa: don't update draw buffer bounds in _mesa_update_state") Signed-off-by: Eric Engestrom <[email protected]>
* i965: perf: add support for GeminilakeLionel Landwerlin2017-06-274-1/+9131
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: perf: add support for KabylakeLionel Landwerlin2017-06-275-1/+20970
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: perf: use gen_device_info rather then brw_contextLionel Landwerlin2017-06-271-2/+2
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: perf: ensure isolated timer reports while idle don't confuse filteringRobert Bragg2017-06-271-1/+17
| | | | | | | | | | | | | | | From experimentation in IGT, we found that the OA unit might label some report as "idle" (using an invalid context ID), right after a report for a given context. Deltas generated by those reports actually belong to the previous context, even though they're not labelled as such. This change makes ensure that while reading OA reports, we only consider the GPU actually idle after 2 reports with an invalid context ID. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: perf: keep on reading reports until delimiting timestampLionel Landwerlin2017-06-271-20/+113
| | | | | | | | | | | | | | | | | | | | | | Due to an underlying hardware race condition, we have no guarantee that all the reports coming from the OA buffer related to the workload we're trying to measure have landed to memory by the time all the work submitted has completed. That means we need to keep on reading the OA stream until we read a report with a timestamp more recent than the timestamp recored by the MI_REPORT_PERF_COUNT at the end of the performance query. v2: fix uninitialized offset variable to 0 (Lionel) v3: rework the reading to avoid blocking the user of the API unless requested (Rob) v4: fix a bug that makes the i965 driver reading the perf stream when not necessary, leading to very long counter accumulation times (Lionel) Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add Gen8+ INTEL_performance_query supportRobert Bragg2017-06-273-33/+288
| | | | | | | | | | Enables access to OA unit metrics on Gen8+ via INTEL_performance_query. v2: make use of new parameters coming from gen_device_info (Lionel) Signed-off-by: Robert Bragg <[email protected]> Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add XML OA metric sets for Gen8+Robert Bragg2017-06-279-14/+65809
| | | | | | | | Also updates Makefile.am to generate corresponding normalization code. Signed-off-by: Robert Bragg <[email protected]> Acked-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add Gen8+ sys_vars for generated OA codeRobert Bragg2017-06-271-0/+3
| | | | | | | | | | | In preparation for adding XML OA metric set descriptions for Gen 8 and 9 which will result in auto generated code that depends on a number of new system variables ($EuSubslicesTotalCount, $EuThreadsCount and $SliceMask) this adds corresponding members to brw->perf.sys_vars. Signed-off-by: Robert Bragg <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* anv/i965: drop libdrm_intel dependency completelyLionel Landwerlin2017-06-271-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | With Ken's work to drop the library dependency on libdrm_intel, we now only depend on libdrm for the kernel uapi headers it provides. It seems like we're better off just embeddeding those headers ourselves, making the lives of people developping news features tightly integrated with the kernel a tiny bit easier. This change also makes it a bit more obvious what cflags/libs are required by the i915 drivers vs i965, by renaming INTEL_CFLAGS/LIBS into I915_CFLAGS/LIBS. Headers were generated from drm-tip on the following commit : commit 6d61e70ccc21606ffb8a0a03bd3aba24f659502b Merge: 338ffbf7cb5e c0bc126f97fb Author: Dave Airlie <[email protected]> Date: Tue Jun 27 07:24:49 2017 +1000 Backmerge tag 'v4.12-rc7' into drm-next v2: Use installed files from the kernel (Daniel Vetter) v3: Use headers from drm-next rather than drm-tip (Dave/Daniel) Signed-off-by: Lionel Landwerlin <[email protected]> Acked-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i915: use different CFLAGS/LIBS variables than i965/anvLionel Landwerlin2017-06-271-2/+2
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965: perf: minimize the chances to spread queries across batchbuffersLionel Landwerlin2017-06-271-0/+8
| | | | | | | | | | | Counter related to timings will be sensitive to any delay introduced by the software. In particular if our begin & end of performance queries end up in different batches, time related counters will exhibit biffer values caused by the time it takes for the kernel driver to load new requests into the hardware. Signed-off-by: Lionel Landwerlin <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Separate gen < 8 and gen >= 8 paths explicitly in wrap_mode()Topi Pohjolainen2017-06-271-3/+3
| | | | | | | | | | | Makes coverity happier. Fix indentation in gen >= 8 block while at it. CID: 1413020 Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i915: On Gen <= 3 there are no array texturesIan Romanick2017-06-264-17/+0
| | | | | Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]>
* i915: On Gen <= 3 there is no W-tilingIan Romanick2017-06-264-29/+9
| | | | | Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]>
* i915: Remove unused fields intel_mipmap_tree::logical_(width|height|depth)0Ian Romanick2017-06-262-11/+0
| | | | | Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]>
* i915: Remove unused field intel_mipmap_tree::array_spacing_lod0Ian Romanick2017-06-261-9/+0
| | | | | Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]>
* i915: On Gen <= 3 there is no multisamplingIan Romanick2017-06-263-38/+9
| | | | | Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]>
* i915: Trivial code reformattingIan Romanick2017-06-261-56/+54
| | | | | Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]>
* i915,i965: Don't condition use of GLSL clear on the current APIIan Romanick2017-06-262-7/+2
| | | | | | | | | | | | | | Meta always sets the API to API_OPENGL_COMPAT, so the current API setting is irrelevant. text data bss dec hex filename 7154994 256860 37332 7449186 71aa62 32-bit i965_dri.so before 7154978 256860 37332 7449170 71aa52 32-bit i965_dri.so after 6788451 328056 50704 7167211 6d5ceb 64-bit i965_dri.so before 6788419 328056 50704 7167179 6d5ccb 64-bit i965_dri.so after Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]>
* drirc: whitelist glthread for a few gamesMarek Olšák2017-06-261-0/+16
| | | | | | | | | | Performance deltas: Alien Isolation: +17% (it varies depending on the location) Borderlands 2: +50% (it varies depending on the location) BioShock Infinite: +76% (benchmark) Civilization 6: +20% (benchmark) Reviewed-by: Timothy Arceri <[email protected]>
* i965/miptree: Rework aux enablingJason Ekstrand2017-06-234-122/+120
| | | | | | | | | | | | | | | | | | This commit replaces the complex and confusing set of disable flags with two fairly straightforward fields which describe the intended auxiliary surface usage and whether or not the miptree supports fast clears. Right now, supports_fast_clear can be entirely derived from aux_usage but that will not always be the case. This commit makes functional changes. One of these changes is that it re-enables multisampled fast-clears which were accidentally disabled in cec30a666930ddb8476a9452a89364a24979ff62 around a year ago. Fixing this improves the SynMark v7 DeferredAA test by around ~3% on some gen9 hardware. This commit also gets us closer to enabling CCS_E for window-system buffers which are Y-tiled. Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Clamp clear colors to the representable rangeJason Ekstrand2017-06-231-0/+40
| | | | | | | | | | | | Starting with Sky Lake, we can clear to arbitrary floats or integers. Unfortunately, the hardware isn't particularly smart when it comes sampling from that clear color. If the clear color is out of range for the surface format, it will happily return whatever we put in the surface state packet unmodified. In order to avoid returning bogus values for surfaces with a limited range, we need to do some clamping. Cc: "17.1" <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Don't bother with HiZ in renderbuffer_move_to_tempJason Ekstrand2017-06-231-4/+0
| | | | | | This function is only used on gen4-5 which don't support HiZ. Reviewed-by: Chad Versace <[email protected]>
* i965/miptree: Rename the non_msrt_mcs functions to _ccsJason Ekstrand2017-06-233-40/+25
| | | | | | | While we're here, we also make the two support checks static since there are no users outside intel_mipmap_tree.c. Reviewed-by: Chad Versace <[email protected]>
* i965/miptree: Delete the layered rendering resolveJason Ekstrand2017-06-231-14/+0
| | | | | | | | | We never fast-clear more than the base slice (LOD 0, layer 0) anyway, so layered rendering without a resolve is always perfectly safe. Should this ever change in the future, we'll have to put some sort of resolve back in but we can cross that bridge when we come to it. Reviewed-by: Chad Versace <[email protected]>
* i965/cnl: Don't write to Cache Mode Register 1 on gen10+Anuj Phogat2017-06-231-2/+4
| | | | | | | | | | | With below optimizations gone in gen10+ we have nothing left out to write to CACHE_MODE_1: Float Blend Optimization Enable: This bit have been removed in gen10+ Partial Resolve Disable in VC: Recommendation is to always set this field to 0 in gen10+ and that's the default value of the bit. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* drirc: Add glsl_correct_derivatives_after_discard for The Witcher 2Edmondo Tommasina2017-06-231-0/+4
| | | | | | | | This fixes the long-standing problem with black transitions in The Wicher 2. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98238 Signed-off-by: Marek Olšák <[email protected]>
* st/dri: add a drirc workaround for Rocket LeagueMarek Olšák2017-06-232-0/+8
| | | | | | | | | | | | | | This needs to be passed to gallium drivers. No game fix is planned at this time. The addition of glsl_correct_derivatives_after_discard is generally a good thing for mesa compatibility with the broader GL driver ecosystem. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100070 Reviewed-by: Nicolai Hähnle <[email protected]>
* i965: Convert upload_default_color to genxml.Rafael Antognolli2017-06-221-77/+85
| | | | | | | | | | This function was moved to genX_state_upload.c but was still not using genxml. By converting it to genxml, we make some things simpler, like setting haswell's border color state, but others are more complex, since the structs used by each gen are different. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* i965: Remove unused code and delete file.Rafael Antognolli2017-06-222-626/+0
| | | | | | | | The sampler state code was all moved to genxml, so we can get rid of these functions and delete the file. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* i965: Convert vs, gs, tcs, tes and cs samplers to genxml.Rafael Antognolli2017-06-223-126/+123
| | | | | | | | Since they just use the code that is already available in genX_state_upload.c, convert them in one batch. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* i965: Convert fs sampler state to use genxml.Rafael Antognolli2017-06-223-23/+540
| | | | | | | | Also convert some auxiliary functions used by it, and copy upload_default_color to genX_state_upload.c. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* i965: Fix -Wunused-variable in gen8_write_pma_stall_bits()Chad Versace2017-06-221-2/+0
| | | | Trivial fix. 'ctx' was unused.
* i965/dri: Add intel_screen param to intel_create_winsys_renderbufferChad Versace2017-06-223-11/+17
| | | | | | | The param is currently unused. It will later be used it to support R8G8B8X8 EGLConfigs on Skylake. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Move brw_context format arrays to intel_screenChad Versace2017-06-224-40/+64
| | | | | | | | | | | | | | | | | | | This allows us to query the driver's supported formats in i965's DRI code, where often there is available a DRIscreen but no GL context. To reduce diff noise, this patch does not completely remove brw_context's format arrays. It just redeclares them as pointers which point to the arrays in intel_screen. Specifically, move these two arrays from brw_context to intel_screen: mesa_to_isl_render_format[] mesa_format_supports_render[] And add a new array to intel_screen, mesa_format_supportex_texture[] which brw_init_surface_formats() copies to ctx->TextureFormatSupported. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Rename some vague format members of brw_contextChad Versace2017-06-229-28/+28
| | | | | | | | | | | | | | | | | | | | | | I'm swimming in a vortex of formats. Mesa formats, isl formats, DRI formats, GL formats, etc. It's easy to misinterpret the following brw_context members unless you've recently read their definition. In upcoming patches, I change them from embedded arrays to simple pointers; after that, even their definition doesn't help, because the MESA_FORMAT_COUNT hint will no longer be present. Rename them to prevent further confusion. While we're renaming, choose shorter names too. -format_supported_as_render_target +mesa_format_supports_render -render_target_format +mesa_to_isl_render_format Reviewed-by: Kenneth Graunke <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-22 17:50:11 +0000