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* intel: Add an assert for glCopyTexSubImage() being called on MSAA buffers.Eric Anholt2013-05-281-0/+6
| | | | | | | | | This is just in case someone else trips over this due to our weird reuse of this code in glBlitFramebuffer(). Reviewed-and-tested-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Acked-by: Paul Berry <[email protected]>
* i965: Allow glCopyTexSubImage() on depth textures.Eric Anholt2013-05-281-5/+0
| | | | | | | | If the hw is pre-gen5 and can't blit depth, it'll cleanly error out. Reviewed-and-tested-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Acked-by: Paul Berry <[email protected]>
* i965: Prefer blorp glBlitFramebuffer() to the glCopyTexSubImage-based blit.Eric Anholt2013-05-281-8/+9
| | | | | | | | | | | | I think we've measured no performance difference from this in the past, except that the blorp code can do things like multisample resolves. Prevents piglit regression in the next commit when a testcase started trying to do a multisampled resolve through the old glCopyTexSubImage() path. Reviewed-and-tested-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Acked-by: Paul Berry <[email protected]>
* i965: Consistently do depth resolves before blitting.Eric Anholt2013-05-282-6/+6
| | | | | | | | | | | | | We were protected for a long time by the fact that depth was Y tiled and you couldn't blit Y. Now that we can blit Y, we were failing to resolve depth in glCopyPixels(). Note in the comment about swrast, that the swrast map path does resolves appropriately already. Reviewed-and-tested-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Acked-by: Paul Berry <[email protected]>
* intel: Make a wrapper for intelEmitCopyBlit using miptrees.Eric Anholt2013-05-285-111/+127
| | | | | | | | | | | | | | I had previously asserted that it was hard to write a useful, simpler blit function, but I think this might be it. This has the side effect of extending the 32k pitch check to a few more places that were missing it. v2: Update comment for being moved inside intel_miptree_blit(). Reviewed-and-tested-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Acked-by: Paul Berry <[email protected]>
* intel: Rename intel_renderbuffer_tile_offsets.Eric Anholt2013-05-283-6/+6
| | | | | | | | This makes it more consistent with intel_miptree_get_tile_offsets(). Reviewed-and-tested-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Acked-by: Paul Berry <[email protected]>
* intel: Reduce intel_renderbuffer_tile_offsets to a thin wrapper.Eric Anholt2013-05-282-28/+7
| | | | | | Reviewed-and-tested-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Acked-by: Paul Berry <[email protected]>
* intel: Make intel_miptree_get_tile_offsets return a page offset.Eric Anholt2013-05-284-10/+26
| | | | | | | | | Right now, the callers in i965 don't expect a nonzero page offset to actually occur (since that's being handled elsewhere), but it seems like a trap to leave it this way. Reviewed-and-tested-by: Ian Romanick <[email protected]> Acked-by: Paul Berry <[email protected]>
* xlib: add null ctx check in glXDestroyContext()Brian Paul2013-05-241-10/+12
| | | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=64934 NOTE: This is a candidate for the stable branches. Reviewed-by: Jose Fonseca <[email protected]>
* i965: Go back to using the kernel SOL reset feature.Kenneth Graunke2013-05-233-8/+7
| | | | | | | | | | | | | | | It turns out the MI_LOAD_REGISTER_IMM approach doesn't work on Haswell, and regressed essentially all the transform feedback Piglit tests. This morally reverts eaa6fbe6d54dc99efac4ab8e800edef65ce8220d. However, the code is still simpler than it was. On BeginTransformFeedback, we simply flush the batch and set the SOL reset flag so that the next batch will start with zeroed offsets. There's still no software counting. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=64887 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Enable guardband clipping on Gen4/5.Chris Forbes2013-05-241-3/+45
| | | | | | | | | | Enables guardband clipping when the viewport covers the entire render target. No piglit regressions on Ironlake. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* intel: Count fragments in our blitter-based glBitmap() path.Eric Anholt2013-05-221-8/+12
| | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=59440 Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Shut up more compiler warnings from vector insert/extract changes.Eric Anholt2013-05-221-0/+8
| | | | | Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Skip etc-to-rgb transcode on BayTrail.Eric Anholt2013-05-201-31/+33
| | | | | | The hardware does it, so no need for this workaround. Reviewed-and-tested-by: Kenneth Graunke <[email protected]>
* i965: Split BeginTransformFeedback hook into Gen6 and Gen7+ variants.Kenneth Graunke2013-05-214-29/+42
| | | | | | | | | | | Most of the work in BeginTransformFeedback is only necessary on Gen6. We may as well just skip it on Gen7+. v2: Add an intel->gen == 6 assert. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Kill software primitive counting entirely.Kenneth Graunke2013-05-216-108/+22
| | | | | | | | | | | | | | | | Now that we have hardware contexts, we don't need to continually reprogram the GS_SVBI_INDEX registers. They're automatically saved and restored with the context, so they can just increment over time. We only need to reset them when starting transform feedback. There's also no reason to delay until the next drawing operation; we can just emit the packet immediately. However, this means we must drop the initialization in brw_invariant_state, as BeginTransformFeedback may occur before the first drawing in a context. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Remove software geometry query code.Kenneth Graunke2013-05-214-71/+0
| | | | | | | | | | EXT_transform_feedback isn't yet supported on Gen4-5, so none of this query code is actually used. This also means we can remove some of the surrounding support code. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Delete unused brw->sol.offset_0_batch_start field.Kenneth Graunke2013-05-213-8/+0
| | | | | | | | This was only used for the the non-hardware context code. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Stop using the kernel SOL reset feature.Kenneth Graunke2013-05-213-10/+8
| | | | | | | | We can just do it ourselves with MI_LOAD_REGISTER_IMM. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Remove dead code for Gen7 SOL without hardware contexts.Kenneth Graunke2013-05-211-15/+0
| | | | | | | | | Failing to get a hardware context now means failing to load the driver, so this code will never get hit. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Add a macro for accessing the SO_WRITE_OFFSET[0-3] registers.Kenneth Graunke2013-05-211-0/+2
| | | | | | | | Using a function-like macro makes it easy to loop over all four streams. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* xlib: check for null ctx pointer in glXIsDirect()Brian Paul2013-05-211-1/+1
| | | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=64745 Note: This is a candidate for the stable branches. Reviewed-by: Jose Fonseca <[email protected]>
* i965: Fix build failureAnuj Phogat2013-05-201-0/+1
| | | | | meta.h should be included in brw_state_upload.c to get access to function _mesa_meta_in_progress().
* i965: Implement transform feedback query support in hardware on Gen6+.Kenneth Graunke2013-05-201-35/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we have hardware contexts and can use MI_STORE_REGISTER_MEM, we can use the GPU's pipeline statistics counters rather than going out of our way to count primitives in software. Aside from being simpler, this also paves the way for Geometry Shaders, which can output an arbitrary number of primitives on the GPU. It will also allow us to use hardware primitive restart when these queries are in use. The GL_TRANSFORM_FEEDBACK_PRIMITIVES_WRITTEN query is easy: it corresponds to the SO_NUM_PRIMS_WRITTEN/SO_NUM_PRIMS_WRITTEN0_IVB counters. The GL_PRIMITIVES_GENERATED query is trickier. Gen provides several statistics registers which /almost/ match the semantics required: - IA_PRIMITIVES_COUNT The number of primitives fetched by the VF or IA (input assembler). This undercounts when GS is enabled, as it can output many primitives. - GS_PRIMITIVES_COUNT The number of primitives output by the GS. Unfortunately, this doesn't increment unless the GS unit is actually enabled, and it usually isn't. - SO_PRIM_STORAGE_NEEDED*_IVB The amount of space needed to write primitives output by transform feedback. These naturally only work when transform feedback is on. We'd also have to add the counters for all four streams. - CL_INVOCATION_COUNT The number of primitives processed by the clipper. This doesn't work if the GS or SOL throw away primitives for rasterizer discard. However, it does increment even if the clipper is in REJECT_ALL mode. Dynamically switching between counters would be painfully complicated, especially since GS, rasterizer discard, and transform feedback can all be switched on and off repeatedly during a single query. The most usable counter is CL_INVOCATION_COUNT. The previous two patches reworked rasterizer discard support so that all primitives hit the clipper, making this work. v2: Occlusion query bug fixes removed and squashed in earlier patches. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Handle rasterizer discard in the clipper rather than GS on Gen6.Kenneth Graunke2013-05-204-40/+11
| | | | | | | | | | | | | | | | This has more of a negative impact than the previous patch, as on Gen6 passing primitives through to the clipper means we actually have to make the GS thread write them to the URB. I don't see another good solution though, and rasterizer discard is not the most common of cases, so hopefully it won't be too terrible. v2: Add a perf_debug; resolve rebase conflicts on the brw dirty flags; remove the rasterizer_discard field from brw_gs_prog_key. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> [v1] Reviewed-by: Paul Berry <[email protected]>
* i965: Handle rasterizer discard in the clipper rather than SOL on Gen7.Kenneth Graunke2013-05-202-7/+11
| | | | | | | | | | | | | | | | | | | | In order to implement the GL_PRIMITIVES_GENERATED query in a sane fashion on our hardware, we can't discard primitives until the clipper. The patch after next explains the rationale. By setting the clipper to REJECT_ALL mode, all primitives get thrown away, so rendering is still appropriately disabled. This may negatively impact performance in the rasterizer discard case, but it's unclear how much and this hasn't been observed to be a bottleneck in any application we've looked at. The clipper is the very next stage in the pipeline, so I don't think it will be terrible. v2: Add a perf_debug; resolve rebase conflicts on the brw dirty flags. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Disable clipper statistics when meta operations are in progress.Kenneth Graunke2013-05-202-4/+9
| | | | | | | | | | | | | | | | | We don't currently use the clipper statistics, but we'll soon use CL_INVOCATIONS_COUNT to implement the GL_PRIMITIVES_GENERATED query. The number of primitives generated is not supposed to be altered during operations such as glGenerateMipmap. Prevents spec/EXT_transform_feedback/generatemipmap prims_generated from breaking when we start using pipeline statistics registers to implement the GL_PRIMITIVES_GENERATED query in a few commits. v2: Use the BRW_NEW_META_IN_PROGRESS flag for correct state handling. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> [v1] Reviewed-by: Paul Berry <[email protected]>
* i965: Create a BRW_NEW_META_IN_PROGRESS state flag.Kenneth Graunke2013-05-202-1/+12
| | | | | | | This will allow us to disable statistics during meta operations. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Add #defines for the pipeline statistics counter registers.Kenneth Graunke2013-05-201-0/+13
| | | | | | | | These come from the Ivybridge PRM, Volume 1, Part 3. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Rely on hardware contexts for query objects on Gen6+.Kenneth Graunke2013-05-205-73/+423
| | | | | | | | | | | | | | | | | | | | | | | | | | | Hardware contexts greatly simplify the query object code. The pipeline statistics counters get saved and restored with the context, which means that we don't need to worry about other workloads polluting them. This means that we can simply write a single pair of values (one at BeginQuery and one at EndQuery) rather than a series of pairs. This also means we don't need to worry about the BO getting full. We also don't need to delay BO allocation and starting snapshot until the first draw. The generation split here is a little off: technically, Ironlake can also support hardware contexts. However, the kernel currently doesn't, and even if it were to do so someday, we'd need to wait a while before bumping the kernel requirement to take advantage of it. v2: Incorporate Paul's feedback. - Clarify which functions are Gen4/5-only via assertions and comments. - Change how driver hook initialization happens. - Update comments. - Squash a bug fix from a later commit here where it belongs. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> [v1] Acked-by: Paul Berry <[email protected]>
* i965: Disable pixel statistics in BLORP.Kenneth Graunke2013-05-202-2/+0
| | | | | | | | | | | | BLORP is used for operations like glClear, glCopyTexImage, and glBlitFramebuffer which aren't supposed to contribute fragments toward occlusion queries. This prevents Piglit tests from breaking in the next commit. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Require hardware contexts (and thus Kernel 3.6) on Gen6+.Kenneth Graunke2013-05-202-8/+17
| | | | | | | | | | | | | | | | | | | | | | | | | Hardware contexts are necessary to reasonably support OpenGL 3.2. In particular, we currently maintain software counters for transform feedback buffer offsets and counters, which relies on knowing the number of primitives generated. Geometry shaders violate that assumption. At the time of writing, Debian has moved to Kernel 3.8, which means most people probably have a newer kernel by now. It's also worth noting that this patch won't land until Mesa 10 which is currently targeted for September. By that point, even more people will have a newer kernel. Also, don't bother trying to allocate contexts on pre-Gen6, as it currently will always fail, and if this changes in the future, we'll need to reevaluate our hw_ctx/gen checks. This patch leaves the code for flagging BRW_NEW_CONTEXT on new batchbuffers if hw_ctx == NULL since that still occurs pre-Gen6. Also remove the Gen7+ check for kernel 3.3, since it's now redundant. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Bump kernel requirement to 3.3 on Ivybridge.Kenneth Graunke2013-05-203-21/+12
| | | | | | | | | | Kernel 3.3 introduced the SOL reset execbuf parameter, needed for GL 3.0 on Ivybridge. Bumping the requirement will give an obvious error message rather than simply reporting GL 2.1. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Add cases for ir_triop_vector_insert that assert.Kenneth Graunke2013-05-202-0/+5
| | | | | | | | | | brw_link_shader() unconditionally calls lower_vector_insert() with true as the second parameter. This means that both constant and variable indexed expressions will get lowered, so we should never see this in the backend. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Add cases for ir_binop_vector_extract that assert.Kenneth Graunke2013-05-202-0/+5
| | | | | | | | | | | | | | | do_vec_index_to_swizzle() should remove any vector extract operations with a constant index. It's unconditionally called from do_common_optimization(). do_vec_index_to_cond_assign() should remove the rest, and it is unconditionally called from brw_link_shader(). This means that we should never see ir_binop_vector_extract in the backend. Silences compiler warnings. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* mesa: Make FinishRenderTexture just take the renderbuffer being finished.Eric Anholt2013-05-173-8/+5
| | | | | | | Now that the rb has a reference to the teximage, we didn't need anything else out of the attachment. Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Track the TexImage being rendered to in the gl_renderbuffer.Eric Anholt2013-05-175-33/+18
| | | | | | | | | We keep having to pass the attachments around with our gl_renderbuffers because that's the only way to find what the gl_renderbuffer actually refers to. This is a step toward removing that (though drivers still need the Zoffset as well). Reviewed-by: Kenneth Graunke <[email protected]>
* radeon: Remove dead radeon_wrap_texture().Eric Anholt2013-05-171-30/+0
| | | | | | I should have killed this in my previous cleanup. Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Make gl_renderbuffers backed by EGL images use FinishRenderTexture.Eric Anholt2013-05-173-10/+11
| | | | | | | | | | | | | This is the opportunity that radeon and intel drivers rely on for flushing render targets that may get reused as textures. Before EGL, that only happened for GL_TEXTURE attachments. Fixes piglits: KHR_gl_renderbuffer_image/renderbuffer-texture OES_EGL_image/renderbuffer-texture NOTE: This is a candidate for the 9.1 branch. Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Don't spam "intelReadPixels: fallback to swrast" in non-PBO case.Kenneth Graunke2013-05-161-11/+10
| | | | | | | | | | | | | | | | When an application is using PBOs, we attempt to use the BLT engine to perform ReadPixels. If that fails due to some restrictions, it's useful to raise a performance warning. In the non-PBO case, we always use a CPU mapping since getting the data into client memory requires a CPU-side copy. This is a very common case, so raising a performance warning is annoying. In particular, apitrace's image dumping code hits this path, causing it to print hundreds of thousands of performance warnings via ARB_debug_output. This tends to obscure actual errors or other important messages. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* intel: Do a depth resolve before copying images between miptrees.Paul Berry2013-05-161-0/+6
| | | | | | | | | | | | | | | | | | | When intel_finalize_mipmap_tree() calls intel_miptree_copy_teximage() to reassemble a depth miptree that has been broken apart into pieces (to deal with misalignment of levels/layers within the miptree), it just copies the depth data, not the HiZ data. This is reasonable, since the alignment restrictions of HiZ are a large part of the reason why the miptree had to be broken apart in the first place. However, in order for the depth copy to be sufficient, we need to do a depth resolve first, to make sure any deferred depth writes that are in the HiZ buffer get performed. Fixes https://bugs.freedesktop.org/show_bug.cgi?id=64662 and https://bugs.freedesktop.org/show_bug.cgi?id=64659. NOTE: This is a candidate for stable release branches. Reviewed-by: Chad Versace <[email protected]>
* i965: Fill in brw_format_for_mesa_format for some non-rendering formats.Eric Anholt2013-05-151-18/+18
| | | | | | | | | This should have no change on driver operation, but it means that when you wonder why some format isn't supported natively, you can just look at the table above, instead of wondering if maybe there's an appropriate entry in the surface formats table that is already supported. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Use native RGB_FLOAT16 support when available.Eric Anholt2013-05-151-1/+1
| | | | | | | | | Previously we would expand it to RGBA_FLOAT16. This format now comes out as framebuffer incomplete, but it seems worth the memory savings if that's what people are asking for (and GL3 does list it under "texture-only" color formats) Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Add support for blitting 6 byte-per-pixel formats.Eric Anholt2013-05-151-7/+14
| | | | | | | The next commit introduces what is apparently our first one, which tripped over this in glReadPixels. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Use the Mesa surface formats for float RGB surfaces.Eric Anholt2013-05-151-2/+2
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Use the new XRGB UNORM formats.Eric Anholt2013-05-151-3/+3
| | | | | | | This is a step on the way to removing some of our code for forcing alpha to 1, but I want easy bisecting so I'll add groups of formats separately. Reviewed-by: Kenneth Graunke <[email protected]>
* radeon: Use accessor for stencil reference valuesChris Forbes2013-05-152-2/+5
| | | | | | | | | | | V2: Drop spurious mask with 0xff. NOTE: This is a candidate for stable branches. Signed-off-by: Chris Forbes <[email protected]> Acked-by: Paul Berry <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* nouveau: Use accessor for stencil reference valuesChris Forbes2013-05-152-2/+5
| | | | | | | | | NOTE: This is a candidate for stable branches. Signed-off-by: Chris Forbes <[email protected]> Acked-by: Paul Berry <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* intel: Use accessor for stencil reference valuesChris Forbes2013-05-153-8/+11
| | | | | | | | | NOTE: This is a candidate for stable branches. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Add missing Haswell GT3 Desktop to IS_HSW_GT3 check.Rodrigo Vivi2013-05-131-2/+2
| | | | | | | NOTE: This is a candidate for stable branches. Signed-off-by: Rodrigo Vivi <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
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