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* i965: more register number assertionsmesa_20090313Brian Paul2009-03-131-0/+7
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* i965: add some register number assertionsBrian Paul2009-03-131-0/+8
| | | | | Haven't seen failures yet, but if/when there are, more investigation will be done.
* i965: remove unused PROGRAM_INTERNAL_PARAM, added commentBrian Paul2009-03-131-3/+1
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* i965: move declarations before codeBrian Paul2009-03-131-6/+6
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* i965: debug code, use gl_register_file typeBrian Paul2009-03-131-1/+7
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* i965: move declaration before codeBrian Paul2009-03-121-2/+1
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* i965: fix const correctnessBrian Paul2009-03-121-1/+1
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* i915: move declarations before codeBrian Paul2009-03-122-4/+4
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* i965: commentsBrian Paul2009-03-121-0/+3
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* i965: fix polygon stipple when rendering to FBORobert Ellison2009-03-121-4/+31
| | | | | | | | | | | | | | | The polygon stipple pattern, like the viewport and the polygon face orientation, must be inverted on the i965 when rendering to a FBO (which itself has an inverted pixel coordinate system compared to raw Mesa). In addition, the polygon stipple offset, which orients the stipple to the window system, disappears when rendering to an FBO (because the window system offset doesn't apply, and there's no associated FBO offset). With these fixes, the conform triangle and polygon stipple tests pass when rendering to texture.
* i965: add support for ATI_envmap_bumpmapRoland Scheidegger2009-03-123-0/+9
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* regenerate glapiRoland Scheidegger2009-03-121-0/+38
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* i965: fix polygon face orientation when rendering to FBORobert Ellison2009-03-111-2/+8
| | | | | | | | | | | | | | In the i965, the FBO coordinate system is inverted from the standard OpenGL/Mesa coordinate system; that means that the viewport and the polygon face orientation have to be inverted if rendering to a FBO. The viewport was already being handled correctly; but polygon face was not. This caused a conform failure when rendering to texture with two-sided lighting enabled. This fixes the problem in the i965 driver, and adds to the comment about the gl_framebuffer "Name" field so that this isn't a surprise to other driver writers.
* intel: include main/viewport.hBrian Paul2009-03-111-0/+1
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* i965: fix lock-ups when GLSL program wrote to gl_FragDepthBrian Paul2009-03-111-1/+27
| | | | | | | It seems the code that set up the FB_WRITE message was incomplete in this case. The number of payload registers was wrong and that caused a hang. It would be good to have a second set of eyes take a look at this...
* i965: more code clean-ups, commentsBrian Paul2009-03-101-4/+11
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* i965: minor code clean-ups, commentsBrian Paul2009-03-101-10/+12
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* i965: use new cast wrappersBrian Paul2009-03-103-9/+16
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* i965: added cast wrappers, commentsBrian Paul2009-03-101-3/+29
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* i965: asst. code clean-ups, commentsBrian Paul2009-03-101-17/+19
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* i965: fix typos in commentsBrian Paul2009-03-101-2/+2
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* xmesa: set back-buffer's drawable fieldBrian Paul2009-03-091-0/+1
| | | | Fixes back-buffer rendering when MESA_BACK_BUFFER=pixmap
* i965: fix cube map lock-up / corruptionBrian Paul2009-03-091-9/+13
| | | | | | If we're using anything but GL_NEAREST sampling of a cube map, we need to use the BRW_TEXCOORDMODE_CUBE texcoord wrap mode. Before this, the GPU would either lock up or subsequent texture filtering would be corrupted.
* fix typo in fragment pipe alu define, should fix dot3_rgb tex combineRoland Scheidegger2009-03-091-1/+1
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* r300: remove assignment to removed StringPos fieldBrian Paul2009-03-071-1/+0
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* mesa: move glViewport and glDepthRange functions into new viewport.c fileBrian Paul2009-03-072-1/+3
| | | | A bit of refactoring with an eye toward ES2 and GL 3.1
* mesa: gl_register_file enum typedefBrian Paul2009-03-072-3/+3
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* mesa: remove GL_MESA_program_debug extensionBrian Paul2009-03-073-8/+0
| | | | This was never fully fleshed out and hasn't been used.
* mesa: remove last of _mesa_unreference_framebuffer() callsBrian Paul2009-03-0718-18/+18
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* r300: shut up valgrindMaciej Cencora2009-03-072-2/+2
| | | | | | It complained about uninitialized values Signed-off-by: Nicolai Haehnle <[email protected]>
* i965: check if we run out of GRF/temp registersBrian Paul2009-03-061-1/+25
| | | | | | | Before this change we would up emitting instructions with invalid register numbers. This typically (but not always) hung the GPU. For now, just prevent emitting bad instructions to avoid hangs. Still need to do some kind of proper error recovery.
* i965: bump up BRW_EU_MAX_INSNBrian Paul2009-03-061-1/+1
| | | | This is the size of the intermediate instruction buffer.
* i965: commentsBrian Paul2009-03-061-0/+2
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* i965: comments and minor clean-upsBrian Paul2009-03-061-3/+43
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* i965: avoid unnecessary calls to brw_wm_is_glsl()Brian Paul2009-03-064-2/+12
| | | | | | | | | This function scans the shader to see if it has any GLSL features like conditionals and loops. Calling this during state validation is expensive. Just call it when the shader is given to the driver and save the result. There's some new/temporary assertions to be sure we don't get out of sync on this.
* r300: fix depth write regression (found by Nicolai Haehnle)Maciej Cencora2009-03-061-3/+10
| | | | Signed-off-by: Nicolai Haehnle <[email protected]>
* r300: enable EXT_fog_coord extensionMaciej Cencora2009-03-062-161/+20
| | | | | | Remove fixed function fog setup. Signed-off-by: Nicolai Haehnle <[email protected]>
* r300: route fog coord and W pos correctlyMaciej Cencora2009-03-062-42/+106
| | | | | | Also cleanup sw tcl vertex buffer setup Signed-off-by: Nicolai Haehnle <[email protected]>
* r300: rewrite and hopefully simplify RS setupMaciej Cencora2009-03-063-213/+225
| | | | | | Testing and regression fixes by Markus Amsler Signed-off-by: Nicolai Haehnle <[email protected]>
* r300: add few macros for RS setupMaciej Cencora2009-03-061-0/+6
| | | | Signed-off-by: Nicolai Haehnle <[email protected]>
* r300: silence valgrindMaciej Cencora2009-03-061-1/+1
| | | | Signed-off-by: Nicolai Haehnle <[email protected]>
* r300: Print reg address when debugging is enabledMaciej Cencora2009-03-061-4/+14
| | | | Signed-off-by: Nicolai Haehnle <[email protected]>
* r300: don't crash on sw tcl hw if point size vertex attrib is sentMaciej Cencora2009-03-061-2/+2
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* intel: Fix bpp setting of blits to 8bpp targets.Eric Anholt2009-03-051-0/+2
| | | | | This was causing hangs in cairogears, as we would blit to the 8bpp target (A8 texture) as 16bpp, and stomp over state objects.
* i965: fix 3DPRIMITIVE batch decode of the vertex count field.Eric Anholt2009-03-051-1/+1
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* i965: Stop dumping programs after the first all-zeroes entry.Eric Anholt2009-03-051-0/+8
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* intel: Add always_flush_batch driconf option for making small batchbuffers.Eric Anholt2009-03-056-1/+25
| | | | | This can improve debugging with INTEL_DEBUG=batch,sync by giving smaller batchbuffers.
* intel: Add always_flush_cache driconf option for debugging cache flush failure.Eric Anholt2009-03-057-2/+42
| | | | | I keep wanting to hack this knob in as a one-time thing, so it seemed useful to have all the time.
* i965: Add a note about why the _NEW_STENCIL is required in draw_buffers.Eric Anholt2009-03-051-0/+5
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* intel: Remove a gratuitous MI_FLUSH after clearing with a blit.Eric Anholt2009-03-051-1/+0
| | | | | The 3D destination shares the same cache so we don't have any trouble with the later commands needing the writes flushed inside of the same batchbuffer.
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