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* r600: use CB_TARGET_MASK instead of CB_SHADER_MASK for setting color maskAndre Maasikas2009-09-291-3/+3
| | | | | | makes blend functions work better Signed-off-by: Dave Airlie <[email protected]>
* r600: user correct alpha blend factorAndre Maasikas2009-09-291-2/+2
| | | | Signed-off-by: Dave Airlie <[email protected]>
* r600: clear position enable bit when when wpos is not used by FPAndre Maasikas2009-09-291-0/+5
| | | | Makes doom3 alot nicer..
* meta: Fix invalid PBO access from DrawPixels when trying to just alloc.Eric Anholt2009-09-281-6/+15
| | | | | | | | | This whole reuse of buffers (TexSubImage instead of TexImage, SubData instead of Data) is bad for hardware drivers, but it's even worse when we accidentally try to access the 2x2 PBO to fill the new 16x16 texture we're creating, producing GL errors. Fixes piglit pbo-drawpixels. Bug #14163.
* intel: Drop my generatemipmap code in favor of the new shared code.Eric Anholt2009-09-288-309/+1
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* intel: Remove some dead metaops code.Eric Anholt2009-09-287-68/+2
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* Merge branch 'mesa_7_6_branch'Brian Paul2009-09-282-1/+5
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| * Merge branch 'mesa_7_5_branch' into mesa_7_6_branchBrian Paul2009-09-281-1/+4
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| | * i915: Fix GetBufferSubData in the case of a system-memory BO.mesa_7_5_2_rc1Eric Anholt2009-09-241-1/+4
| | | | | | | | | | | | Bug #23760 (crashes in wine)
| | * intel: Mark the FBO as incomplete if there's no intel_renderbuffer for it.Eric Anholt2009-09-211-0/+5
| | | | | | | | | | | | | | | | | | | | | This happens to rendering with textures with a border, which had resulted in a segfault on dereferencing the irb. (cherry-picked from commit 8bba183b9eeb162661a287bf2e118c6dd419dd24)
| * | intel: Handle GL_RGB8 for glCopyTex(Sub)Image.Michel Dänzer2009-09-251-0/+1
| | | | | | | | | | | | Avoids an unnecessary fallback.
* | | r600 : Enable draw_prim.Richard Li2009-09-271-2/+0
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* | | Merge branch 'asm-shader-rework-2'Ian Romanick2009-09-251-0/+1
|\ \ \ | | | | | | | | | | | | | | | | Conflicts: src/mesa/shader/program_parse.tab.c
| * \ \ Merge branch 'master' into asm-shader-rework-2Ian Romanick2009-09-1080-1771/+2506
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: src/mesa/shader/lex.yy.c src/mesa/shader/program_parse.tab.c src/mesa/shader/program_parse.tab.h
| * | | | Enable GL_NV_fragment_program_option for software renderingIan Romanick2009-09-031-0/+1
| | | | | | | | | | | | | | | | | | | | At this point the extension is not fully implemented.
* | | | | radeon: Fix newlines.Michal Krol2009-09-251-14/+14
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* | | | | Merge branch 'mesa_7_6_branch'Brian Paul2009-09-255-20/+10
|\ \ \ \ \ | | |_|/ / | |/| | | | | | | | | | | | | | | | | | Conflicts: src/mesa/drivers/dri/intel/intel_clear.c
| * | | | intel: Flush the batch when we're about to subdata into a VBO.mesa_7_6_rc1Eric Anholt2009-09-242-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes the clears in openarena with the new metaops clear code, and the new piglit vbo-subdata-sync test. Bug #23857.
| * | | | i965: Clean up some mess with the batch cache.Eric Anholt2009-09-243-18/+5
| | | | | | | | | | | | | | | | | | | | | | | | | Its flagging of extra state that's already flagged by the vtbl new_batch when appropriate was confusing my tracking down of the OA clear bug.
* | | | | mesa: _mesa_meta_GenerateMipmap() now workingBrian Paul2009-09-241-33/+172
| | | | | | | | | | | | | | | | | | | | | | | | | Handles GL_TEXTURE_1D, GL_TEXTURE_2D, GL_TEXTURE_CUBE_MAP. But GL_TEXTURE_3D and texture borders not supported yet.
* | | | | Merge branch 'mesa_7_6_branch'Brian Paul2009-09-244-2/+25
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: src/mesa/vbo/vbo_exec_array.c
| * | | | i965: Emit zero initialization for NV VP temporaries as required.Eric Anholt2009-09-241-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is similar to what r300 does inside the driver, but I've added it as a generic option since it seems most hardware will want it. Fixes piglit nv-init-zero-reg.vpfp and nv-init-zero-addr.vpfp.
| * | | | i965: Remove assert about NV_vp now that it somewhat works.Eric Anholt2009-09-241-2/+0
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| * | | | i965: Load NV program matrices when required.Eric Anholt2009-09-241-0/+3
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| * | | | intel: use default array/element buffers in intel_generate_mipmap()Brian Paul2009-09-241-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If there happened to be a bound VBO when intel_generate_mipmap() was called we blew up because of a bad vertex array pointer. Fixes regnumonline, bug 23859.
* | | | | Merge branch 'mesa_7_6_branch'Pauli Nieminen2009-09-242-6/+7
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| * | | | radeon: Fix scissors for r600 KMS.Pauli Nieminen2009-09-242-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Radeon generic scissors code had problem that some of code was using exclusive and some inclusive bottom right corner. Only r600 driver is using exclusive coordinate so changed generic code to pass inclusive coordinate and r600 driver changes BR coordinate to be exclusive.
* | | | | Merge branch 'mesa_7_6_branch'Brian Paul2009-09-241-2/+16
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: src/mesa/drivers/dri/r600/r700_assembler.c src/mesa/drivers/dri/r600/r700_chip.c src/mesa/drivers/dri/r600/r700_render.c src/mesa/drivers/dri/r600/r700_vertprog.c src/mesa/drivers/dri/r600/r700_vertprog.h src/mesa/drivers/dri/radeon/radeon_span.c
| * | | | r600: add support for CUBE textures, also TXPAndre Maasikas2009-09-242-47/+263
| | | | | | | | | | | | | | | | | | | | seems to work here ...
| * | | | r600: fix typo in the last commitAlex Deucher2009-09-241-5/+5
| | | | | | | | | | | | | | | | | | | | 128 gprs, 256 reg-based consts
| * | | | r600: various cleanupsAlex Deucher2009-09-243-45/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - max texture size is 8k, but mesa doesn't support that at the moment. - attempt to set shader limits to what the hw actually supports - clean up some old r300 cruft - no need to explicitly disable irqs. This is fixed in the drm now. Signed-off-by: Alex Deucher <[email protected]>
| * | | | r600: fix some issues with LIT instructionAndre Maasikas2009-09-241-33/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - MUL_LIT is ALU.Trans instruction - some Trans instructions can take 3 arguments - don't clobber dst.x, use dst.z as temp, it'll get written correct value in last insn - respect source swizzles
| * | | | r600: fix point sizesAlex Deucher2009-09-241-4/+4
| | | | | | | | | | | | | | | | | | | | registers takes radius
| * | | | r600: fix polygon offsetAlex Deucher2009-09-241-3/+8
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| * | | | radeon: don't build non-r600 span code on r600Alex Deucher2009-09-241-1/+5
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| * | | | r600: minor span cleanupsAlex Deucher2009-09-241-4/+3
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| * | | | r600: support position_invariant programsAndre Maasikas2009-09-241-12/+18
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| * | | | r600: add span support for 1D tilesAlex Deucher2009-09-243-1/+223
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1D tile span support for depth/stencil/color/textures Z and stencil buffers are always tiled, so this fixes sw access to Z and stencil buffers. color and textures are currently linear, but this adds span support when we implement 1D tiling. This fixes the text in progs/demos/engine and progs/tests/z*
| * | | | r600: fix warningAlex Deucher2009-09-241-0/+1
| | | | | | | | | | | | | | | | | | | | Noticed by rnoland on IRC.
| * | | | r600: fix texcoords from constantsAndre Maasikas2009-09-241-40/+52
| | | | | | | | | | | | | | | | | | | | with some minor updates from Richard.
| * | | | r600: enable caching of vertex programsAndre Maasikas2009-09-246-62/+110
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| * | | | r600: check if textures are actually enabled before submissionAlex Deucher2009-09-242-56/+64
| | | | | | | | | | | | | | | | | | | | noticed by taiu on IRC.
| * | | | r600: fix ftp for dri1Alex Deucher2009-09-241-3/+4
| | | | | | | | | | | | | | | | | | | | We use t->bo for dri1 since r600 uses CS for dri1.
| * | | | r600: don't setup hardware state if TFPDave Airlie2009-09-241-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | if we have a BO here it means TFP and we should have set it up already. tested by b0le on #radeon
| * | | | r600: fix dri2 clippingAlex Deucher2009-09-241-2/+2
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| * | | | r300: fallback to software rendering if we are out of free texcoordsMaciej Cencora2009-09-231-2/+16
| | | | | | | | | | | | | | | | | | | | Fixes #22741
* | | | | r600 : fix draw_prim bug: vertex fetcher setting.Richard Li2009-09-241-3/+16
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* | | | | r600 : disable draw_prim for now.Richard Li2009-09-241-1/+4
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* | | | | r600: fix up ordering of functions in draw prims pathAlex Deucher2009-09-231-16/+15
| | | | | | | | | | | | | | | | | | | | | | | | | Shaders and IB need to be updated and allocated before calling validatebuffers.
* | | | | r600: fix r700PredictRenderSize for draw prims pathAlex Deucher2009-09-231-7/+12
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