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* meta: (trivial) remove accidental double semicolonRoland Scheidegger2014-10-011-1/+1
* i965: Enable EXT_framebuffer_multisample_blit_scaled for gen8Anuj Phogat2014-10-011-2/+1
* meta: Implement ext_framebuffer_multisample_blit_scaled extensionAnuj Phogat2014-10-012-13/+199
* i965: Initialize the SampleMap{2,4,8}x variablesAnuj Phogat2014-10-013-0/+55
* i965: Drop CACHE_NEW_VS_PROG from the gen7_sf_state atom.Kenneth Graunke2014-10-011-1/+1
* i965: Drop brwBindProgram driver hook.Kenneth Graunke2014-10-011-20/+0
* i965: Add missing /* BRW_NEW_FRAGMENT_PROGRAM */ comments.Kenneth Graunke2014-10-013-6/+7
* i965: Use "1ull" instead of "1" in BRW_NEW_* defines.Kenneth Graunke2014-10-011-32/+32
* i965: Use ~0ull when flagging all BRW_NEW_* dirty flags.Kenneth Graunke2014-10-013-4/+4
* i965: Fix INTEL_DEBUG=state to work with 64-bit dirty bits.Kenneth Graunke2014-10-011-16/+7
* i965: Delete CACHE_NEW_BLORP_CONST_COLOR_PROG.Kenneth Graunke2014-10-012-3/+0
* i965: Fix typo in commentChris Forbes2014-10-011-1/+1
* i965: Fix spelling of GEN7_SAMPLER_EWA_ANISOTROPIC_ALGORITHMChris Forbes2014-10-012-2/+2
* i965/fs: Fix the buildJason Ekstrand2014-09-301-1/+1
* i965/fs: Fix an uninitialized value warningsJason Ekstrand2014-09-301-3/+4
* i965/fs: Emit compressed BFI2 instructions on Gen > 7.Matt Turner2014-09-301-1/+1
* i965/fs: Allow SIMD16 borrow/carry/64-bit multiply on Gen > 7.Matt Turner2014-09-301-3/+3
* i965/fs: Set MUL source type to W/UW in 64-bit mul macro on Gen8.Matt Turner2014-09-301-1/+22
* i965/fs: Optimize sqrt+inv into rsq.Matt Turner2014-09-301-0/+11
* i965/vec4: Optimize sqrt+inv into rsq.Matt Turner2014-09-301-0/+11
* i965/vec4: Call opt_algebraic after opt_cse.Matt Turner2014-09-301-1/+1
* i965/fs: Extend predicated break pass to predicate WHILE.Matt Turner2014-09-301-0/+36
* i965/fs: Don't make a name for a vector splitting temporaryIan Romanick2014-09-301-3/+8
* glsl: Make ir_variable::num_state_slots and ir_variable::state_slots privateIan Romanick2014-09-303-9/+9
* i965/brw_reg: Make the accumulator register take an explicit width.Jason Ekstrand2014-09-303-10/+15
* mesa: Drop the always-software-primitive-restart paths.Eric Anholt2014-09-301-8/+0
* i965/fs: Properly calculate the number of instructions in calculate_register_...Jason Ekstrand2014-09-301-1/+3
* i965/fs: Use the GRF for FB writes on gen >= 7Jason Ekstrand2014-09-306-71/+142
* i965/fs: Handle COMPR4 in LOAD_PAYLOADJason Ekstrand2014-09-302-1/+36
* i965/fs: Constant propagate into LOAD_PAYLOADJason Ekstrand2014-09-301-0/+1
* i965/fs: Add split_virtual_grfs and compute_to_mrf after lower_load_payloadJason Ekstrand2014-09-301-0/+2
* i965/fs: Add a an optional source to the FS_OPCODE_FB_WRITE instructionJason Ekstrand2014-09-304-29/+28
* i965/fs: Use the GRF for UNTYPED_SURFACE_READ instructionsJason Ekstrand2014-09-304-16/+24
* i965/fs: Use the GRF for UNTYPED_ATOMIC instructionsJason Ekstrand2014-09-306-25/+36
* i965/fs: Add a function for getting a component of a 8 or 16-wide registerJason Ekstrand2014-09-301-0/+10
* i965/fs: Use the instruction execution size directly for texture generationJason Ekstrand2014-09-301-3/+10
* i965/fs: Use exec_size instead of force_uncompressed in dump_instructionJason Ekstrand2014-09-301-6/+7
* i965/fs: Use instruction execution sizes instead of heuristicsJason Ekstrand2014-09-303-23/+10
* i965/fs: Use instruction execution sizes to set compression stateJason Ekstrand2014-09-301-6/+19
* i965/fs: Remove unneeded uses of force_uncompressedJason Ekstrand2014-09-303-25/+9
* i965/fs: Derive force_uncompressed from instruction exec_sizeJason Ekstrand2014-09-301-0/+3
* i965/fs: Make fs_reg::effective_width take fs_inst* instead of fs_visitor*Jason Ekstrand2014-09-303-37/+43
* i965/fs: Better guess the width of LOAD_PAYLOADJason Ekstrand2014-09-301-2/+9
* i965/fs: Add an exec_size field to fs_instJason Ekstrand2014-09-305-32/+126
* i965/fs: Determine partial writes based on the destination widthJason Ekstrand2014-09-302-5/+3
* i965/fs: Fix a bug in register coalesceJason Ekstrand2014-09-301-0/+17
* i965/fs: Rework GEN5 texturing code to use fs_reg and offset()Jason Ekstrand2014-09-301-39/+38
* i965/fs_reg: Allocate double the number of vgrfs in SIMD16 modeJason Ekstrand2014-09-309-157/+371
* i965/fs: Handle printing of registers better.Jason Ekstrand2014-09-301-2/+6
* i965: Explicitly set widths on gen5 math instruction destinations.Jason Ekstrand2014-09-301-1/+1
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