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* i965/fs: Emit fixed width memory fence opcode regardless of the dispatch width.Francisco Jerez2016-05-271-2/+3
* i965/fs: Return 32 bit mask from fs_builder::sample_mask().Francisco Jerez2016-05-271-1/+3
* i965/fs: Emit fixed-width null register regardless of the dispatch width.Francisco Jerez2016-05-271-8/+4
* i965/fs: Fix half() to handle more exotic register files.Francisco Jerez2016-05-271-21/+4
* i965/fs: Fix horiz_offset() to handle ARF and HW GRF register files.Francisco Jerez2016-05-271-4/+10
* i965/fs: Clean up remaining uses of fs_inst::reads_flag and ::writes_flag.Francisco Jerez2016-05-275-24/+12
* i965/fs: Keep track of flag dependencies with byte granularity during schedul...Francisco Jerez2016-05-271-10/+31
* i965/fs: Track flag register liveness with byte granularity.Francisco Jerez2016-05-272-25/+9
* i965/fs: Define methods to calculate the flag subset read or written by an fs...Francisco Jerez2016-05-272-11/+67
* i965/fs: Expose arbitrary channel execution groups to the IR.Francisco Jerez2016-05-276-32/+35
* i965/ir: Make BROADCAST emit an unmasked single-channel move.Francisco Jerez2016-05-274-3/+17
* i965/fs: Allow specifying arbitrary quarter control to FIND_LIVE_CHANNEL.Francisco Jerez2016-05-271-7/+12
* i965/fs: Allow specifying arbitrary execution sizes up to 32 to FIND_LIVE_CHA...Francisco Jerez2016-05-271-8/+17
* i965/fs: Lower 32-wide scratch writes in the generator.Francisco Jerez2016-05-271-6/+24
* i965/fs: Implement scratch reads and writes of 4 GRFs at a time.Francisco Jerez2016-05-273-21/+18
* i965/eu: Fix Gen7+ DP scratch message size calculation on Gen7.Francisco Jerez2016-05-271-1/+4
* i965/eu: Set execution size explicitly for memory fence send message.Francisco Jerez2016-05-271-4/+7
* i965/eu: Consider QtrCtrl 3Q-4Q in typed surface message descriptor setup.Francisco Jerez2016-05-271-6/+6
* i965/fs: Clean up remaining uses of dispatch_width in the generator.Francisco Jerez2016-05-273-9/+8
* i965/eu: Remove brw_codegen::compressed and ::compressed_stack.Francisco Jerez2016-05-273-11/+5
* i965/eu: Use current exec size instead of p->compressed in surface message ge...Francisco Jerez2016-05-271-6/+8
* i965/fs: No need to reset predicate control after emitting some instructions.Francisco Jerez2016-05-271-2/+0
* i965/fs: Pass current execution size to brw_IF() and brw_DO().Francisco Jerez2016-05-271-2/+2
* i965/eu: Stop using p->compressed to specify the exec size of control flow in...Francisco Jerez2016-05-271-13/+11
* i965/fs: Extend region width calculation to allow arbitrary execution sizes.Francisco Jerez2016-05-271-16/+23
* i965/fs: Pass the compression mode to brw_reg_from_fs_reg().Kenneth Graunke2016-05-271-5/+6
* i965/fs: Simplify per-instruction compression control setup in generator.Francisco Jerez2016-05-271-27/+17
* i965/fs: No need to set compression control at the top of generate_code().Francisco Jerez2016-05-271-2/+0
* i965/eu: Fix a bunch of compression control bugs in the generator.Francisco Jerez2016-05-272-10/+9
* i965/eu: Define alternative interface for setting compression and group contr...Francisco Jerez2016-05-272-0/+75
* i965/fs: Remove FS_OPCODE_PACK_STENCIL_REF virtual instruction.Francisco Jerez2016-05-275-52/+2
* i965/fs: Remove extract virtual opcodes.Francisco Jerez2016-05-275-53/+9
* i965: Define brw_int_type() helper.Francisco Jerez2016-05-271-0/+20
* i965/fs: Remove manual splitting of DDY ops in the generator.Francisco Jerez2016-05-271-37/+1
* i965/fs: Remove manual unrolling of BFI instructions from the generator.Francisco Jerez2016-05-271-34/+2
* i965/fs: Drop Gen7 CMP SIMD unrolling workaround from the generator.Francisco Jerez2016-05-271-36/+10
* i965/fs: Drop lowering code for a few three-source instructions from the gene...Francisco Jerez2016-05-271-47/+4
* i965/fs: Set default access mode to Align1 for all instructions in the genera...Francisco Jerez2016-05-271-0/+1
* i965/fs: Remove handcrafted math SIMD lowering from the generator.Francisco Jerez2016-05-272-101/+21
* i965/fs: Limit SIMD width of various virtual opcodes to the maximum supported...Francisco Jerez2016-05-271-5/+40
* i965/fs: Lower LOAD_PAYLOAD instructions of unsupported width.Francisco Jerez2016-05-271-0/+19
* i965/fs: Lower DDY instructions to SIMD8 during SIMD lowering timeFrancisco Jerez2016-05-271-0/+29
* i965/fs: Apply usual FPU-like execution size restrictions to MULH.Francisco Jerez2016-05-271-1/+2
* i965/fs: Calculate maximum execution size of MOV_INDIRECT correctly.Francisco Jerez2016-05-271-9/+3
* i965/fs: Assert that IF instruction with embedded compare has legal exec_size.Francisco Jerez2016-05-271-0/+4
* i965/fs: Implement HSW BFI exec size workarounds in the SIMD lowering pass.Francisco Jerez2016-05-271-2/+8
* i965/fs: Implement workaround for IVB CMP dependency race in the SIMD lowerin...Francisco Jerez2016-05-271-1/+17
* i965/fs: Enforce common regioning restrictions by SIMD splitting.Francisco Jerez2016-05-271-20/+104
* i965/fs: Enforce extended math exec size limits during SIMD lowering.Francisco Jerez2016-05-271-10/+24
* i965/fs: Handle SAMPLEINFO consistently like other texturing instructions.Francisco Jerez2016-05-274-17/+15
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