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* mesa/colormac: introduce inline helper for 4 unclamped float to ubyte.Dave Airlie2011-09-145-29/+9
| | | | | | | | | This introduces an UNCLAMPED_FLOAT_TO_UBYTE x 4 inline function, as suggested by Brian. It uses it in a few places I noticed from previous color changes, and also some core mesa places. I haven't updated other places yet. Signed-off-by: Dave Airlie <[email protected]>
* mesa: introduce a clear color union to be used for int/unsigned buffersDave Airlie2011-09-149-43/+59
| | | | | | | | | | This introduces a new gl_color_union union and moves the current ClearColorUnclamped to use it, it removes current ClearColor completely and renames CCU to CC, then all drivers are modified to expected unclamped floats instead. also fixes st to use translated color in one place it wasn't. Signed-off-by: Dave Airlie <[email protected]>
* dri: Remove all extension enabling utility functionsIan Romanick2011-09-094-148/+0
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* swrast-dri: Remove call to driInitExtensionsIan Romanick2011-09-091-2/+0
| | | | | | | | The only purpose this call served in the DRI swrast driver was to initialize the remap table. Core Mesa already does the dispatch offset remapping for every function that could possibly ever be supported. There's no need to continue using that cruft in the driver.
* radeon: Enable extensions by just setting the flagsIan Romanick2011-09-091-59/+39
| | | | | | | | | | | | | | | | | Core Mesa already does the dispatch offset remapping for every function that could possibly ever be supported. There's no need to continue using that cruft in the driver. Since the call to _mesa_enable_imaging_extensions (via driInitExtensions) is removed, EXT_blend_color, EXT_blend_logic_op, and EXT_blend_minmax are no longer advertised. These all resulted in software fallbacks, so their loss will not be mourned. EXT_blend_subtract is, however, explicitly added to the list. GL_FUNC_SUBTRACT is fully accelerated, but GL_FUNC_REVERSE_SUBTRACT (still) results in a software fallback. Cc: Alex Deucher <[email protected]> Cc: Dave Airlie <[email protected]>
* r600: Enable extensions by just setting the flagsIan Romanick2011-09-091-105/+61
| | | | | | | | | | | | | | | | Core Mesa already does the dispatch offset remapping for every function that could possibly ever be supported. There's no need to continue using that cruft in the driver. Since the call to _mesa_enable_imaging_extensions (via driInitExtensions) is removed, EXT_blend_color is explicitly added to the list. EXT_blend_logic_op is removed from the list of extensions because blend factors and separate blend equations are not handled correctly. Cc: Alex Deucher <[email protected]> Cc: Dave Airlie <[email protected]>
* r300: Enable extensions by just setting the flagsIan Romanick2011-09-091-100/+62
| | | | | | | | | | | | | | | | | | | Core Mesa already does the dispatch offset remapping for every function that could possibly ever be supported. There's no need to continue using that cruft in the driver. Since the call to _mesa_enable_imaging_extensions (via driInitExtensions) is removed, EXT_blend_color is explicitly added to the list. EXT_blend_logic_op is removed from the list of extensions because blend factors and separate blend equations are not handled correctly. Based on feedback from Roland Scheidegger. Cc: Dave Airlie <[email protected]> Cc: Alex Deucher <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Corbin Simpson <[email protected]>
* r200: Enable extensions by just setting the flagsIan Romanick2011-09-091-107/+63
| | | | | | | | | | | | | | | | | | Core Mesa already does the dispatch offset remapping for every function that could possibly ever be supported. There's no need to continue using that cruft in the driver. Since the call to _mesa_enable_imaging_extensions (via driInitExtensions) is removed, EXT_blend_color is explicitly added with a dependency on the drmSupportsBlendColor flag. EXT_blend_logic_op is removed from the list of extensions because blend factors and separate blend equations are not handled correctly. Based on feedback from Roland Scheidegger. Cc: Alex Deucher <[email protected]> Cc: Dave Airlie <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* nouveau: Enable extensions by just setting the flagsIan Romanick2011-09-093-43/+28
| | | | | | | | | | | | | | | | | Core Mesa already does the dispatch offset remapping for every function that could possibly ever be supported. There's no need to continue using that cruft in the driver. Since the call to _mesa_enable_imaging_extensions (via driInitExtensions) is removed, EXT_blend_color, EXT_blend_minmax, and EXT_blend_subtract are explicitly added to the list. EXT_blend_logic_op is removed from the list of extensions because blend factors and separate blend equations are not handled correctly. Cc: Ben Skeggs <[email protected]> Reviewed-by: Francisco Jerez <[email protected]> Cc: Viktor Novotný <[email protected]>
* intel: Move S3TC extension enable bits to intel_extensions.cIan Romanick2011-09-092-7/+8
| | | | | Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Enable extensions by just setting the flagsIan Romanick2011-09-091-191/+98
| | | | | | | | | | | | Core Mesa already does the dispatch offset remapping for every function that could possibly ever be supported. There's no need to continue using that cruft in the driver. EXT_blend_logic_op is removed from the list of extensions because blend factors and separate blend equations are not handled correctly. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* spantmp2: Silence many "warning: unused parameter ‘ctx’"Ian Romanick2011-09-091-0/+20
| | | | | Not all drivers use ctx in LOCAL_VARS, so '(void) ctx;' is added to all the function templates to make GCC happy.
* swrast-dri: Silence several "warning: unused parameter"Ian Romanick2011-09-091-0/+14
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* dri: Silence several "warning: unused parameter"Ian Romanick2011-09-091-0/+8
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* dri_util: Silence several "warning: unused parameter"Ian Romanick2011-09-091-1/+11
| | | | The parameters can't be removed because they are part of the DRI ABI.
* intel: Silence "intel/intel_fbo.h:105:4: warning: comparison of unsigned ↵Ian Romanick2011-09-091-3/+3
| | | | | | | | | | | expression < 0 is always false" The test was of an enum, attIndex, which should be unsigned. The explicit check for < 0 was replaced with a cast to unsigned in an assertion that attIndex is less than the size of the array it will be used to index. Reviewed-by: Eric Anholt <[email protected]>
* intel: Silence several "warning: unused parameter"Ian Romanick2011-09-091-0/+2
| | | | | | | Trivially silence the compiler by adding '(void) foo;' for each unused parameter. These parameters could not be removed. They are part of interface used elsewhere in Mesa, and some of the other customers actually use these parameters.
* intel: Silence several "warning: unused parameter"Ian Romanick2011-09-091-13/+4
| | | | | | | | | | | | | | | | | | | | | The internalFormat, format, and type parameters were not used by either try_pbo_upload or try_pbo_zcopy, so remove them. The width parameter was also not used by try_pbo_zcopy (because it doesn't actually copy anything), so remove it too. Eric Anholt notes: The current structure of this code is so hateful I can't bring myself to say anything about whether changing the current code is good or bad. I have a dream that one call would try to make a surface (miptree/region) out of the PBO, then we'd see about whether it matches up nicely and zero-copy/blit using that. That would be reusable for texsubimage, which is currently awful in this respect. At some point we should revisit this code with pitchforks and torches.
* intel: Silence "warning: unused parameter ‘depth0’"Ian Romanick2011-09-093-7/+4
| | | | | | | | | | The depth0 parameter was not used in intel_miptree_create_for_region, so remove it. All of the places that call this function, pass 1 for that parameter, and the place where it looks like it should have been used (the call to intel_miptree_create_internal) also had 1 hard coded. Reviewed-by: Eric Anholt <[email protected]>
* intel: Silence "warning: unused parameter ‘target’"Ian Romanick2011-09-093-13/+5
| | | | | | | | | The GLenum target parameter was not used in intel_copy_texsubimage, so remove it. Also remove the GLenum internalFormat parameter. Each caller just copied this out of the intel_texture_image that is already passed to intel_copy_texsubimage. Reviewed-by: Eric Anholt <[email protected]>
* intel: Silence several "warning: unused parameter"Ian Romanick2011-09-096-53/+30
| | | | | | The intel_context and tiling parameters were not used by any if the i9[14]5_miptree_layout or the functions they call, and the tiling parameter was not used by brw_miptree_layout. Remove the unnecessary parameters.
* intel: Silence "warning: unused parameter ‘fb’"Ian Romanick2011-09-094-7/+7
| | | | | | The gl_framebuffer was not used in intel_draw_buffer, so remove it. Reviewed-by: Eric Anholt <[email protected]>
* intel: Silence "warning: unused parameter ‘intel’"Ian Romanick2011-09-093-11/+7
| | | | The intel_context was not used in any of these functions, so remove it.
* intel: Silence several "warning: unused parameter"Ian Romanick2011-09-091-22/+38
| | | | | | | | | Also clean-up some of the naming, etc. in intel_buffer_object_purgeable. 'intel' is usually used as the name of an intel_context pointer, and intel_obj is usually used as the name of an intel_*_obj pointer. These changes were suggested by Eric Anholt. Reviewed-by: Eric Anholt <[email protected]>
* intel: Silence many "intel_batchbuffer.h:97:39: warning: comparison between ↵Ian Romanick2011-09-091-2/+3
| | | | | | | | | | | | | | | | | | | | | signed and unsigned integer expressions" v2: Remove the assertion in intel_batchbuffer_space: assert((intel->batch.state_batch_offset - intel->batch.reserved_space) >= intel->batch.used*4); After reviewing all the places where this is called, I'm (fairly) comfortable that this assertion was redundant. Having the assertion adds ~20KiB to a driver build: text data bss dec hex filename 903173 26392 1552 931117 e352d i965_dri.so 924093 26392 1552 952037 e86e5 i965_dri.so Based on feedback from Eric Anholt. Reviewed-by: Eric Anholt <[email protected]>
* nouveau: remove target parameter from nouveau_bufferobj_map_range()Brian Paul2011-09-091-1/+1
| | | | | This was missed back when the target parameter was removed from all the buffer-related driver hooks.
* i965/vs: Allow copy propagation on GRFs.Eric Anholt2011-09-081-1/+6
| | | | | Further reduces instruction count by 4.0% in 40.7% of the vertex shaders.
* i965/vs: Clear tracked copy propagation values whose source gets overwritten.Eric Anholt2011-09-081-3/+12
| | | | | This only occurs for GRFs, and hasn't mattered until now because we only copy propagated non-GRFs.
* i965/vs: Add support for copy propagation of the UNIFORM and ATTR files.Eric Anholt2011-09-083-1/+72
| | | | Removes 2.0% of the instructions from 35.7% of vertex shaders in shader-db.
* i965/vs: Add constant propagation to a few opcodes.Eric Anholt2011-09-085-0/+281
| | | | | | | | | | | This differs from the FS in that we track constants in each destination channel, and we we have to look at all the swizzled source channels. Also, the instruction stream walk is done in an O(n) manner instead of O(n^2). Across shader-db, this reduces 8.0% of the instructions from 60.0% of the vertex shaders, leaving us now behind the old backend by 11.1% overall.
* i965/vs: Keep track of indices into a per-register array for virtual GRFs.Eric Anholt2011-09-082-0/+15
| | | | | | | | | | | | Tracking virtual GRFs has tension between using a packed array per virtual GRF (which is good for register allocation), and sparse arrays where there's an element per actual register (so the first and second column of a mat2 can be distinguished inside of an optimization pass). The FS mostly avoided the need for this second sparse array by doing virtual GRF splitting, but that meant that instances where virtual GRF splitting didn't work, instructions using those registers got much less optimized.
* i965/vs: Switch to the new VS backend by default.Eric Anholt2011-09-081-1/+1
| | | | | | | | | | | Now instead of env INTEL_NEW_VS=1 to get it, you need INTEL_OLD_VS=1 to not get it. While it's not quite to the same codegen efficiency as the old backend, it is not regressing piglit on G965 and G45, and actually fixing bugs on gen6, and the remaining codegen quality regressions all appear tractable. Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vs: Add support for overflowing the number of available push constants.Eric Anholt2011-09-083-0/+87
| | | | | | | | Fixes glsl-vs-uniform-array-4. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=33742 Reviewed-by: Ian Romanick <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965/vs: Pack uniform registers before optimizationEric Anholt2011-09-081-1/+1
| | | | | | | | | We don't expect uniform accesses to generally go away from being dead code at this point, and we will want to have uniforms packed before spilling them out to pull constants when we are forced to do that. Reviewed-by: Ian Romanick <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965/vs: When failing due to lack of spilling, don't continue on.Eric Anholt2011-09-081-0/+1
| | | | | | | | Fixes assertion failure from double-free in oglc glsl-arrayobject constructor.declaration.structure Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vs: Fix variable indexed array access with more than one array.Eric Anholt2011-09-081-1/+1
| | | | | | | | | The offset to the arrays after the first was mis-scaled, so we'd go access off the end of the surface and read 0s. Fixes glsl-vs-uniform-array-3. Reviewed-by: Ian Romanick <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965/vs: Add annotation to more of the URB write.Eric Anholt2011-09-082-1/+5
| | | | | | | | While we had nice debug output for most of the instruction stream, it was terminated by a series of anonymous MOVs and a send. Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: add support for __DRI_IMAGE_FORMAT_ABGR8888Chia-I Wu2011-09-094-0/+27
| | | | | | | | | | | It maps to MESA_FORMAT_RGBA8888_REV. Surfaces of the format can only be sampled from but not render to. Only i915 is tested. Reviewed-by: Eric Anholt <[email protected]> [olv: add a check in intel_image_target_renderbuffer_storage]
* meta: added _mesa_meta_GetTexImage()Brian Paul2011-09-083-1/+232
| | | | | If the texture is compressed, call the meta decompress_texture_image() function. Otherwise, call the core _mesa_get_teximage() function.
* meta: move texcoord setup into setup_texture_coords()Brian Paul2011-09-081-92/+176
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* i965/fs: Implement ir_u2f opcode.Kenneth Graunke2011-09-071-1/+1
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Fix disassembly for intdiv/intmod math functions.Kenneth Graunke2011-09-071-2/+2
| | | | | | | | The opcodes and strings were reversed. Quotient means division, and modulus means remainder. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Use proper texture alignment units for cubemaps on Gen5+.Kenneth Graunke2011-09-071-1/+4
| | | | | | | | | In particular, S3TC compressed textures need align_h == 4. Fixes skybox errors in Quake 4 and FEAR. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34628 Signed-off-by: Kenneth Graunke <[email protected]>
* i965/vs: Fix point size handling on gen4.Eric Anholt2011-09-061-4/+5
| | | | | | Fixes glsl-vs-point-size. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vs: Use write commits on scratch writes in pre-gen6.Eric Anholt2011-09-061-2/+22
| | | | | | | This is required to ensure ordering between reads and writes within a thread. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vs: Fix setup of scratch space pointer on pre-gen6.Eric Anholt2011-09-061-0/+10
| | | | | | | We were failing to relocate, so on the first draw run our scratch would tend to get written to 0x0. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vs: Fix message setup for array read/writes on pre-gen6.Eric Anholt2011-09-061-18/+14
| | | | | | | | We were passing an MRF as the source argument, instead of using the implied move and putting the MRF number in the proper place in the instruction encoding. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vs: Fix constant-indexed array read/write addresses on pre-gen6.Eric Anholt2011-09-061-1/+1
| | | | | | The second vertex was getting a garbage index. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vs: Add support for vector comparison ops resulting in bool cond codes.Eric Anholt2011-09-062-21/+33
| | | | | | Fixes a giant pile of VS tests on gen4. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vs: Make pre-gen6 math operate in vector mode instead of scalar.Eric Anholt2011-09-061-1/+1
| | | | | | | | | | | On the old backend, we used scalar mode because Mesa IR math is result.xyzw = math(op0.xxxx), which matched up well. However, in GLSL IR we do things like result.xy = math(op0.xy), so we want vector mode. For the common case of result.x = math(op0.x), performance will be the same (no cost for un-executed channels), though result.xyzw = math(op0.xxxx) would be worse. Reviewed-by: Kenneth Graunke <[email protected]>
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