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* r300c: do not advertise half float vertex on RV3xx, RS4xx, RC4xxMarek Olšák2010-08-072-2/+2
| | | | | | | Fixes a hardlock. NOTE: this is a candidate for the 7.8 branch, provided the half float vertex is really implemented there.
* r600c: tiling require drm 2.6.0, not 2.5.0Alex Deucher2010-08-051-1/+1
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* r600: add support for getting the tiling config via drm ioctl (v2)Alex Deucher2010-08-051-0/+57
| | | | | | | | Needed for the the 2D tiling span functions. v2: rebase on new kernel, mesa changes Signed-off-by: Alex Deucher <[email protected]>
* r600: add new relocs for tiling supportAlex Deucher2010-08-052-18/+39
| | | | Signed-off-by: Alex Deucher <[email protected]>
* r600: add span support for 2D tilingAlex Deucher2010-08-054-5/+210
| | | | | | | Requires tiling config ioctl support from the drm to use. kms only. Signed-off-by: Alex Deucher <[email protected]>
* intel: Check for a NULL src buffer prior to bltChris Wilson2010-08-051-1/+1
| | | | | | This can only happen along a malloc failure path, but check anyway. Signed-off-by: Chris Wilson <[email protected]>
* intel: Check for region allocation failure.Chris Wilson2010-08-051-0/+6
| | | | Signed-off-by: Chris Wilson <[email protected]>
* dri/nouveau: Don't try to validate uninitialized teximages.Francisco Jerez2010-08-051-4/+4
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* dri/nv20: Fix some PGRAPH_ERRORs seen with DATA_CHECK enabled.Francisco Jerez2010-08-052-2/+6
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* dri/nouveau: Fix up software mipmap generation.Francisco Jerez2010-08-052-5/+51
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* r300/compiler: Remove unnecessary header.Vinson Lee2010-08-041-1/+0
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* intel: Remove unnecessary header.Vinson Lee2010-08-041-1/+0
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* r600: relax stride/alignment requirements for verticesAndre Maasikas2010-08-043-20/+14
| | | | | | | | | | seems hw can do unaligned accesses and unaligned strides removes extra conversion when using vbo's however I needed to switch 3 component byte format to 4 component formats for tests to pass. Somewhat sililar to GL_SHORT fix done earlier removes assert and gains +2 piglit especially draw-vertices
* r300/compiler: Always unroll loops when doing loop emulation.Tom Stellard2010-08-034-11/+14
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* r300/compiler: r500 hw support for break and continue in loops.Tom Stellard2010-08-0310-167/+282
| | | | | | | The BGNLOOP and ENDLOOP instructions are now being used correctly, which makes break and continue possible. The deadcode pass has been modified to handle breaks, and the compiler is more careful about which loops are unrolled.
* r300/compiler: KILP may not always be inside an IF statement.Tom Stellard2010-08-031-9/+14
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* r300/compiler: Don't unroll loops with continue or break.Tom Stellard2010-08-031-1/+12
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* radeon: Add DRI2 flush extension support, so we synchronize properly.Mario Kleiner2010-08-0213-10/+98
| | | | | | | | | | | | | | When a DRI2 swap buffer is pending we need to make sure we have the flush extension so radeon doesn't resume rendering to or reading from the not yet blitted front buffer. This fixes: https://bugs.freedesktop.org/show_bug.cgi?id=28341 https://bugs.freedesktop.org/show_bug.cgi?id=28410 Signed-off-by: Jerome Glisse <[email protected]> Signed-off-by: Mario Kleiner <[email protected]>
* Revert "radeon: Add DRI2 flush extension to so we synchronize properly."Jerome Glisse2010-08-0210-77/+0
| | | | This reverts commit 8446f257b3e3ca4a3eb2c79bc357e46343e04e87.
* radeon: Add DRI2 flush extension to so we synchronize properly.Mario Kleiner2010-08-0210-0/+77
| | | | | | | | | | | | | | | | | When DRI2 swap buffer is pending (copy buffer not pageflipping) we need to make sure we have the flush extension so radeon doesn't resume rendering on the not yet blitted front buffer. Modified version of Jerome's patch to add flush extension in the correct place. This prepares a possible fix for: https://bugs.freedesktop.org/show_bug.cgi?id=28341 https://bugs.freedesktop.org/show_bug.cgi?id=28410 Signed-off-by: Jerome Glisse <[email protected]> Signed-off-by: Mario Kleiner <[email protected]>
* r600: fix sin,cos functions on r600Andre Maasikas2010-08-021-9/+133
| | | | | | | | | | | r600 doesnt need the same normalization as r700 - instead it requires range to be truncated to -pi..pi I left the range trunc also effective on r700 althouch according the docs it has sufficent range (-512*PI, +512*PI). The instructions seem to be used not too often to cause perf loss because of this Based on patches and testing by Conn Clark and Alain Perrot
* mesa: Remove inclusion of compiler.h from mtypes.h.Vinson Lee2010-07-312-0/+5
| | | | | | | mtypes.h does not use any symbols from compiler.h. Also add the required headers for files that depended on symbols from compiler.h but were indirectly including compiler.h through mtypes.h.
* intel: Add missing header to intel_context.c.Vinson Lee2010-07-301-0/+1
| | | | | Fixes "implicit declaration of function _mesa_get_incomplete_framebuffer" warning.
* intel: Add missing header.Vinson Lee2010-07-291-0/+1
| | | | Add context.h for NEED_SECONDARY_COLOR symbol.
* dri: Add missing header to dri_metaops.c.Vinson Lee2010-07-291-0/+1
| | | | Add context.h for FLUSH_VERTICES symbol.
* intel: Declare the various tracked state variables using "extern"Kristian Høgsberg2010-07-291-62/+62
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* intel: Don't depend on context config values when picking texture formatsKristian Høgsberg2010-07-291-24/+12
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* r600: since 8744c36e added asserts - use another random register for shader ↵Andre Maasikas2010-07-291-1/+1
| | | | with no output
* intel: Implement EGL_KHR_surfaceless extensionKristian Høgsberg2010-07-281-7/+20
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* intel: Remove unused intel/server filesKristian Høgsberg2010-07-275-397/+2
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* i965: Fix reversed naming of the operations in compute-to-mrf optimization.Eric Anholt2010-07-263-6/+11
| | | | | Also fix up comments, so that the difference between the two passes is clarified.
* i965: Clean up a few magic numbers to use brw_defines.h defs.Eric Anholt2010-07-263-18/+20
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* i965: Use MIN2, MAX2 instead of rolling our own.Eric Anholt2010-07-261-15/+12
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* i965: Fold the "is arithmetic" bit of 965 opcodes into the opcode list.Eric Anholt2010-07-261-50/+26
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* i965: Remove some duped register size/count definitionsEric Anholt2010-07-262-34/+26
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* i965: Move the GRF-to-MRF optimizations to brw_optimize.c.Eric Anholt2010-07-263-619/+618
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* i965: Improve (i.e. remove) some grf-to-mrf unnecessary movesBenjamin Segovia2010-07-261-2/+626
| | | | | | | | | | | | | | | | | | | | | | | | | Several routines directly analyze the grf-to-mrf moves from the Gen binary code. When it is possible, the mov is removed and the message register is directly written in the arithmetic instruction Also redundant mrf-to-grf moves are removed (frequently for example, when sampling many textures with the same uv) Code was tested with piglit, warsow and nexuiz on an Ironlake machine. No regression was found there Note that the optimizations are *deactivated* on Gen4 and Gen6 since I did test them properly yet. No reason there are bugs but who knows The optimizations are currently done in branch free programs *only*. Considering branches is more complicated and there are actually two paths: one for branch free programs and one for programs with branches Also some other optimizations should be done during the emission itself but considering that some code is shader between vertex shaders (AOS) and pixel shaders (SOA) and that we may have branches or not, it is pretty hard to both factorize the code and have one good set of strategies
* i965: Allow VS MOVs to use immediate constants.Eric Anholt2010-07-261-0/+1
| | | | | Clarifies program assembly, and with a little tweak to always use constant_map, we could cut down on constant buffer payload.
* i965: Cleanly fail programs with unsupported array access.Eric Anholt2010-07-231-1/+28
| | | | | This should be more useful for developers and for bug triaging than just generating wrong code.
* i965: Add support for VS relative addressing of temporary arrays.Eric Anholt2010-07-231-2/+49
| | | | Fixes glsl-vs-arrays. Bug #27388.
* i965: Respect VS/VP point size result when enabled.Eric Anholt2010-07-221-3/+4
| | | | Fixes glsl-vs-point-size.
* i965: Fix the disasm output for da16 src widths.Eric Anholt2010-07-221-1/+1
| | | | | | This has confused me twice now. It's a fixed width of 4 (usually a region description of <4,4,1>), not 1. If it was 1, we'd have been skipping all over register space.
* i965: Avoid extra MOV in VS indirect register reads.Eric Anholt2010-07-221-15/+16
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* i965: Fix up VS temporary array access for fixed index offset != 0.Eric Anholt2010-07-221-1/+1
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* r600: Flip point sprite coordinates when rendering to an FBO.Henri Verbeet2010-07-221-1/+3
| | | | This supersedes http://lists.freedesktop.org/archives/mesa-dev/2010-July/001442.html.
* i965: In the VS, multiply the address reg by the appropriate register size.Eric Anholt2010-07-211-27/+14
| | | | | | | | | | | | The ARL value is increments of vec4 in the register file. But PROGRAM_TEMPORARY or PROGRAM_INPUT are stored as vec4s interleaved between the two verts being executed (thus a vec8 each), compared to PROGRAM_STATE_VAR being packed vec4s. Fixes: glsl-vs-arrays-2 glsl-vs-mov-after-deref (without regressing glsl-vs-arrays-3)
* i965: Clean up brw_dp_READ_4_vs() now that it has fewer options to support.Eric Anholt2010-07-213-52/+31
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* i965: Support relative addressed VS constant reads using the appropriate msg.Eric Anholt2010-07-213-31/+66
| | | | | The previous support was overly complicated by trying to use the same 1-OWORD message for both offsets.
* i965: Fix the DP read msg_control definitions other than plain OWORD.Eric Anholt2010-07-211-6/+16
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* i965: Clean up dead code from the VS get_constant/get_reladdr_constant split.Eric Anholt2010-07-211-3/+1
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