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* i965: Don't add barrier deps for FB write messages.Matt Turner2016-03-301-1/+2
* i965: Add and use is_scheduling_barrier() function.Matt Turner2016-03-301-4/+17
* i965: Remove NOP insertion kludge in scheduler.Matt Turner2016-03-301-20/+5
* i965: Assert that an instruction is not inserted around itself.Matt Turner2016-03-301-0/+4
* i965: Relax restriction on scheduling last instruction.Matt Turner2016-03-301-20/+3
* i965/vec4/tcs: Set conditional mod on TCS_OPCODE_SRC0_010_IS_ZERO.Matt Turner2016-03-302-2/+3
* Revert "i965: Don't add barrier deps for FB write messages."Matt Turner2016-03-301-4/+3
* i965: Simplify full scheduling-barrier conditions.Matt Turner2016-03-301-27/+8
* i965: Remove incorrect cycle estimates.Matt Turner2016-03-301-10/+0
* glsl: add transform feedback buffers to resource listTimothy Arceri2016-03-311-1/+1
* mesa: split transform feedback buffer into its own structTimothy Arceri2016-03-313-7/+7
* glsl: use bitmask of active xfb buffer indicesTimothy Arceri2016-03-311-1/+1
* i965: Don't inline intel_batchbuffer_require_space().Matt Turner2016-03-302-26/+28
* meta: use _mesa_prepare_mipmap_levels()Brian Paul2016-03-291-24/+8
* xlib: add support for GLX_ARB_create_contextBrian Paul2016-03-293-0/+77
* i965: Don't use CUBE wrap modes for integer formats on IVB/BYT.Kenneth Graunke2016-03-291-1/+5
* Revert "i965: Set address rounding bits for GL_NEAREST filtering as well."Kenneth Graunke2016-03-291-6/+3
* i965: Set address rounding bits for GL_NEAREST filtering as well.Kenneth Graunke2016-03-281-3/+6
* i965: Always use BRW_TEXCOORDMODE_CUBE when seamless filtering.Kenneth Graunke2016-03-281-3/+1
* i965: Fix brw_render_cache_set_check_flush's PIPE_CONTROLs.Kenneth Graunke2016-03-282-3/+22
* i965: Whack UAV bit when FS discards and there are no color writes.Kenneth Graunke2016-03-281-2/+7
* mesa: optionally associate a gl_program to ATI_fragment_shaderMiklós Máté2016-03-271-0/+3
* mesa: replace gl_context->Multisample._Enabled with _mesa_is_multisample_enab...Bas Nieuwenhuizen2016-03-246-12/+14
* i965/peephole_ffma: Don't fuse exact addsJason Ekstrand2016-03-231-1/+3
* i965/fs: Don't constant-fold RCPJason Ekstrand2016-03-221-15/+0
* i965: Remove the RCP+RSQ algebraic optimizationsJason Ekstrand2016-03-222-22/+0
* i965: Have NIR lower flrp on pre-GEN6 vec4 backendIan Romanick2016-03-221-2/+26
* i965: fix invalid memory writeMarc-André Lureau2016-03-211-1/+1
* i965: Fix assert conditions for src/dst x/y offsetsAnuj Phogat2016-03-211-3/+3
* i965/blorp: Make BlitFramebuffer() do sRGB encoding in ES 3.x.Kenneth Graunke2016-03-211-1/+4
* i965/blorp: Refactor sRGB encoding/decoding.Kenneth Graunke2016-03-214-11/+23
* meta: Make BlitFramebuffer() do sRGB encoding in ES 3.x.Kenneth Graunke2016-03-213-9/+43
* i965: Stop XY clipping point and line primitives.Kenneth Graunke2016-03-181-1/+7
* i965: Scissor to the viewport when rendering points/lines.Kenneth Graunke2016-03-182-5/+8
* i965: Include the viewport in the scissor rectangle.Kenneth Graunke2016-03-181-4/+4
* i965: Introduce an is_drawing_lines() helper.Kenneth Graunke2016-03-181-0/+30
* i965: Move is_drawing_points to brw_state.h.Kenneth Graunke2016-03-182-24/+24
* i965: Fix gl_TessLevelOuter[] for isolines.Kenneth Graunke2016-03-182-6/+22
* i965: Decode non-normalized coordinates bit in SAMPLER_STATE.Kenneth Graunke2016-03-181-2/+3
* i965: Account for TES in is_drawing_points().Kenneth Graunke2016-03-181-1/+8
* nir: add a bit_size parameter to nir_ssa_dest_initConnor Abbott2016-03-171-2/+5
* nir: rename nir_const_value fields to include bitsize informationIago Toral Quiroga2016-03-176-63/+63
* nir: update opcode definitions for different bit sizesConnor Abbott2016-03-171-0/+18
* i965/nir: fix check to resolve booleans to work with sized nir_alu_typeSamuel Iglesias Gonsálvez2016-03-171-1/+1
* i965/nir: Lower nir compute shader shared variablesJordan Justen2016-03-173-0/+11
* i965: Skip execution size adjustment for instructions of width 4Iago Toral Quiroga2016-03-171-1/+13
* i965/vec4/gen6: fix exec_size for MOV with a width of 4 in generate_gs_ff_sync()Samuel Iglesias Gonsalvez2016-03-171-1/+3
* i965/vec4/gen6: fix exec_size for instructions with destination width of 4Samuel Iglesias Gonsalvez2016-03-171-0/+6
* i965/vec4/gen6: fix exec_size for instructions with width of 4 in generate_gs...Samuel Iglesias Gonsalvez2016-03-171-0/+3
* i965/gs/gen6: fix execsize for instructions with width of 4 in gen6_sol_progr...Samuel Iglesias Gonsalvez2016-03-171-1/+10
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