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* xmlpool: remove the clean targetEmil Velikov2015-04-011-6/+4
| | | | | | | | ... by folding it into CLEANFILES. Don't worry about $(LANG) as it is essentially the first folder of $(POS). With the latter already handled. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* xmlpool: don't forget to ship the MOSEmil Velikov2015-04-011-1/+8
| | | | | | | | | | | | This will allow us to finally remove python from the build time dependencies list. Considering that you're building from a release tarball of course :-) Cc: Bernd Kuhls <[email protected]> Reported-by: Bernd Kuhls <[email protected]> Cc: "10.5" <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* osmesa: don't try to bundle osmesa.def SConscriptEmil Velikov2015-04-011-2/+0
| | | | | | | | Both of which were removed with commit 69db422218b(scons: Don't build osmesa.) Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* i965: Handle scratch accesses where reladdr also points to scratch spaceIago Toral Quiroga2015-04-012-26/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a problem when we have IR like this: (array_ref (var_ref temps) (swiz x (expression ivec4 bitcast_f2i (swiz xxxx (array_ref (var_ref temps) (constant int (2)) ) )) )) ) ) where we are indexing an array with the result of an expression that accesses the same array. In this scenario, temps will be moved to scratch space and we will need to add scratch reads/writes for all accesses to temps, however, the current implementation does not consider the case where a reladdr pointer (obtained by indexing into temps trough a expression) points to a register that is also stored in scratch space (as in this case, where the expression used to index temps access temps[2]), and thus, requires a scratch read before it is accessed. v2 (Francisco Jerez): - Handle also recursive reladdr addressing. - Do not memcpy dst_reg into src_reg when rewriting reladdr. v3 (Francisco Jerez): - Reduce complexity by moving recursive reladdr scratch access handling to a separate recursive function. - Do not skip demoting reladdr index registers to scratch space if the top level GRF has already been visited. v4 (Francisco Jerez) - Remove redundant checks. - Simplify code by making emit_resolve_reladdr return a register with the original src data except for reg, reg_offset and reladdr. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89508 Reviewed-by: Francisco Jerez <[email protected]>
* egl: add initial EGL_MESA_image_dma_buf_export v2.4Dave Airlie2015-04-011-2/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | At the moment to get an EGL image to a dma-buf file descriptor, you have to use EGL_MESA_drm_image, and then use libdrm to convert this to a file descriptor. This extension just provides an API modelled on EGL_MESA_drm_image, to return a dma-buf file descriptor. v2: update spec for new API proposal add internal queries to get the fourcc back from intel driver. v2.1: add gallium pieces. v2.2: add offsets to spec and API, rename fd->fds, stride->strides in API. rewrite spec a bit more, add some q/a v2.3: add modifiers to query interface and 64-bit type for that (Daniel Stone) specifiy what happens to num fds vs num planes differences. (Chad Versace) v2.4: fix grammar (Daniel Stone) Signed-off-by: Dave Airlie <[email protected]>
* i965/state: Remove brw->state.dirtyJordan Justen2015-03-312-7/+0
| | | | | | | | | We now use brw->NewGLState and brw->ctx.NewDriverState instead. Suggested-by: Kenneth Graunke <[email protected]> Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/state: Don't use brw->state.dirty.mesaJordan Justen2015-03-315-12/+11
| | | | | | | | | | | | | | | Now, we only use brw->NewGLState. I used this bash & sed command in the i965 directory: for file in *.[ch] *.[ch]pp; do sed -i -e 's/brw->state\.dirty\.mesa/brw->NewGLState/g' $file done Followed by manual changes to brw_state_upload.c. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/state: Don't use brw->state.dirty.brwJordan Justen2015-03-3133-83/+82
| | | | | | | | | | | | | | | Now, we only use ctx->NewDriverState. I used this bash & sed command in the i965 directory: for file in *.[ch] *.[ch]pp; do sed -i -e 's/state\.dirty\.brw/ctx.NewDriverState/g' $file done Followed by manual changes to brw_state_upload.c. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/state: Add compute pipeline with empty atom listsJordan Justen2015-03-313-1/+37
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/state: Only upload render programs for render state uploadsJordan Justen2015-03-311-20/+25
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/state: Create separate dirty state bits for each pipelineJordan Justen2015-03-312-27/+75
| | | | | | | | | | | | | | | | | | When clearing the state for a pipeline, we will save changed state for the other pipelines. v3: * Adjust brw_upload_pipeline_state * Don't pull pipeline state bits into common state bits * Don't clear pipeline state bits * Adjust 'clear' phase * brw_clear_dirty_bits is now brw_render_state_finished * Move cross-pipeline state flagging to brw_pipeline_state_finished * Move pipeline clears to brw_pipeline_state_finished Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/state: Support multiple pipelines in brw->num_atomsJordan Justen2015-03-312-39/+65
| | | | | | | | | | | | | | | | | brw->num_atoms is converted to an array, but currently just an array of length 1. Adds brw_copy_pipeline_atoms which copies the atoms for a pipeline, and sets brw->num_atoms[p] for pipeline p. v2: * Rename brw->atoms[] to render_atoms * Rename brw_add_pipeline_atoms to brw_copy_pipeline_atoms * Rename brw_pipeline_first_atom to brw_get_pipeline_atoms Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/state: Rename brw_clear_dirty_bits to brw_render_state_finishedJordan Justen2015-03-313-3/+3
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/state: Rename brw_upload_state to brw_upload_render_stateJordan Justen2015-03-313-10/+11
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Allow CSE to handle MULs with negated arguments.Matt Turner2015-03-311-5/+37
| | | | | | | | | | | | | | | | | | | | | mul x, -y is equivalent to mul -x, y; and mul x, y is the negation of mul x, -y. With NIR: total instructions in shared programs: 6167779 -> 6161193 (-0.11%) instructions in affected programs: 983511 -> 976925 (-0.67%) helped: 4106 HURT: 16 GAINED: 18 LOST: 7 Without NIR: total instructions in shared programs: 6192323 -> 6185299 (-0.11%) instructions in affected programs: 987875 -> 980851 (-0.71%) helped: 4146 HURT: 16 GAINED: 16 LOST: 0
* i965: Mark brw_inst_bits' brw_inst* parameter const.Matt Turner2015-03-311-12/+12
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/skl: Avoid using the 1D stencil layout for stencil-only imagesNeil Roberts2015-03-311-1/+2
| | | | | | | | | | | | | Commit cf67ca9ffa9 made the layouting code pick a special layout for 1D images on Skylake. This should not be used for depth and stencil buffers because these need to be treated as 2D tiled images. However the patch was missing a check for images with a base format of GL_STENCIL_INDEX. In practice I don't think it's currently possible to hit this because Mesa doesn't support GL_ARB_texture_stencil8 and it's not possible to create a 1D renderbuffer, but it'll be good to be ready for when the extension is supported. Reviewed-by: Anuj Phogat <[email protected]>
* i965/nir: Use NIR for ARB_vertex_program support on Gen8+.Kenneth Graunke2015-03-271-4/+10
| | | | | | | | | | | Everything is already in place; we simply have to take the scalar code generation path. This gives us SIMD8 VS programs, instead of SIMD4x2. v2: Rebase on the patch that drops brw->gen >= 8. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Connor Abbott <[email protected]>
* i965: Move env_var_as_boolean to intel_debug.c.Kenneth Graunke2015-03-273-22/+29
| | | | | | | I need to use this in brw_vec4.cpp, so it can't be static anymore. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Add ARB_fragment_program support to the NIR backend.Kenneth Graunke2015-03-272-26/+51
| | | | | | | | | | | | | | | | | | | | | Use prog_to_nir where we would normally call glsl_to_nir, handle program parameter lists, and skip a few things that don't exist. Using NIR generates much better shader code than Mesa IR, since we get real optimizations, as opposed to prog_optimize: total instructions in shared programs: 314007 -> 279892 (-10.86%) instructions in affected programs: 285173 -> 251058 (-11.96%) helped: 2001 HURT: 67 GAINED: 4 LOST: 7 v2: Change early return in nir_setup_uniforms to if/else (Jordan). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Connor Abbott <[email protected]>
* i965/skl: Don't use the PMA depth stall workaroundBen Widawsky2015-03-271-1/+6
| | | | | | | | | | | | | | The PMA depth stall must be enabled (optimization turned off) under certain circumstances on gen8. This was supposedly fixed for Gen9, which means we do not need to check, or toggle the state. The hardware is supposed to enable the hardware optimization by default, unlike BDW, so we also don't need to set it at init. For whatever reason this improves stability on ETQW with the bug mentioned below. References: https://bugs.freedesktop.org/show_bug.cgi?id=89039 (doesn't fix) Signed-off-by: Ben Widawsky <[email protected]> Tested-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/skl: Disable partial resolve in VCBen Widawsky2015-03-272-0/+11
| | | | | | | | | | | | | | | | | | | | | Recomendation [sic] is to set this field to 1 always. Programming it to default value of 0, may have -ve impact on performance for MSAA WLs. Another don't suck bit which needs to get set. The patch wasn't as well tested as I would have liked, primarily I don't have perf numbers for it, but it's getting to a point where it is in danger of being lost. v2: v1 was a mix of two patches. Since 0x7004 is masked, we only need to set it once at initialization and make sure the pma workaround doesn't set the mask bit (which it doesn't). Move LRI to init gpu state (Ken) Add a comment. Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965: Drop unnecessary brw->gen >= 8 check from scalar VS code.Kenneth Graunke2015-03-251-1/+1
| | | | | | | brw->scalar_vs already implies that brw->gen >= 8. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/fs: Implement texture projection support.Kenneth Graunke2015-03-251-1/+10
| | | | | | | | | | | | | Our fragment program backend implements support for TXP directly, and there's no NIR lowering pass to remove the projection. When we switch fragment program support over to NIR, we need to support it somehow. It's easy enough to support directly. v2: Split out offset/tex_offset rename (requested by Jordan). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/fs: Rename offset to tex_offset to avoid shadowing offset().Kenneth Graunke2015-03-251-4/+4
| | | | | | | | | | fs_visitor::nir_emit_texture() created an fs_reg variable called offset, which shadowed the offset() helper function in brw_ir_fs.h. Rename the variable to tex_offset so we can still call offset(). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* scons: Don't build osmesa.Jose Fonseca2015-03-253-56/+0
| | | | | | | | | There doesn't seem much interest on osmesa on Windows, particularly classic osmesa. If there is indeed interest in osmesa on Windows, we should instead integrate src/gallium/targets/osmesa into SCons. Reviewed-by: Brian Paul <[email protected]>
* glsl: Allow vector logic ops to be generated.Matt Turner2015-03-241-6/+3
| | | | | | | They're not accessible from the source language, but optimizations are allowed to generate them. Reviewed-by: Ian Romanick <[email protected]>
* i965: add the remaining files to the tarballEmil Velikov2015-03-241-0/+3
| | | | | Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Fix handling of multiple register reads and writes in ↵Francisco Jerez2015-03-231-7/+15
| | | | | | dead_code_eliminate(). Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Calculate live intervals with subregister granularity.Francisco Jerez2015-03-232-33/+46
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Define helpers to calculate the common live interval of a range ↵Francisco Jerez2015-03-234-29/+31
| | | | | | | | | of variables. These will be especially useful when we start keeping track of liveness information for each subregister. Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Define helper functions to convert a register to a variable index.Francisco Jerez2015-03-234-28/+34
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Don't lose the force_writemask_all flag during CSE.Francisco Jerez2015-03-231-0/+3
| | | | | | | And set it in the MOV instructions that copy the temporary to the original destination if the generator instruction had it set. Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Fix handling of multiple register reads and writes in opt_cse().Francisco Jerez2015-03-231-8/+17
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Fix handling of multiple register reads and writes during copy ↵Francisco Jerez2015-03-231-3/+6
| | | | | | propagation. Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Fix handling of multiple register reads and writes in ↵Francisco Jerez2015-03-231-9/+6
| | | | | | split_virtual_grfs(). Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Fix handling of multiple register reads and writes in ↵Francisco Jerez2015-03-231-14/+10
| | | | | | opt_register_coalesce(). Reviewed-by: Matt Turner <[email protected]>
* i965: Define method to check whether a backend_reg is inside a given range.Francisco Jerez2015-03-233-4/+11
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Remove dependency of vec4_live_variables on the visitor.Francisco Jerez2015-03-232-7/+8
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Trivial copy propagate clean-up.Francisco Jerez2015-03-231-5/+6
| | | | | | | Fix typo and punctuation in a comment, break long line and add space before curly bracket. Reviewed-by: Abdiel Janulgue <[email protected]>
* i965/vec4: Add argument index and type checks to SEL saturate propagation.Francisco Jerez2015-03-231-1/+4
| | | | | | | SEL saturate propagation already implicitly relies on these assumptions. Reviewed-by: Abdiel Janulgue <[email protected]>
* i965/vec4: Fix broken saturate mask check in copy propagation.Francisco Jerez2015-03-231-4/+11
| | | | | | | | | | | try_copy_propagate() was checking the bit of the saturate mask for the arg-th component of the source to decide whether the whole source should be saturated (WTF?). We need to swizzle the original saturate mask and check that for all enabled channels the saturate flag is either set or unset, as we cannot saturate a subset of destination components only. Reviewed-by: Abdiel Janulgue <[email protected]>
* i965/vec4: Don't lose copy propagation saturate bits for not written components.Francisco Jerez2015-03-231-1/+1
| | | | Reviewed-by: Abdiel Janulgue <[email protected]>
* Revert "i965/vec4: Don't lose the saturate modifier in copy propagation."Francisco Jerez2015-03-231-1/+1
| | | | | | | | | This reverts commit 0dfec59a2785cf7a87ee5128889ecebe810b611b. The change prevented propagation of copies with the saturate flag set, making the whole saturate mask tracking completely useless. A proper fix follows. Reviewed-by: Abdiel Janulgue <[email protected]>
* i965/vec4: Remove unused method definition.Francisco Jerez2015-03-231-1/+0
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Some more trivial swizzle clean-up.Francisco Jerez2015-03-235-30/+11
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Improve src_reg/dst_reg conversion constructors.Francisco Jerez2015-03-231-26/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This simplifies the src_reg/dst_reg conversion constructors using the swizzle utils introduced in a previous patch. It also makes them more useful by changing their semantics slightly: dst_reg(src_reg) used to set the writemask to XYZW if the src_reg swizzle was anything other than XXXX, which was almost certainly not what the caller intended if the swizzle was non-trivial. After this patch the same components that are present in the swizzle will be enabled in the resulting writemask. src_reg(dst_reg) used to set the first components of the swizzle to the enabled components of the writemask and then replicate the last enabled component to fill the swizzle, which, in cases where the writemask didn't have exactly the first n components set, would in general not be compatible with the original dst_reg. E.g.: | ADD(tmp, src_reg(tmp), src_reg(1)); would *not* do what one would expect (add one to each of the enabled components of tmp) if tmp didn't have a writemask of the described form (e.g. YZ, YW, XZW would all fail). This pattern actually occurs in many different places in the VEC4 back-end, it's a wonder that it hasn't caused piglit failures until now. After this patch src_reg(dst_reg) will construct a swizzle with each enabled component at its natural position (e.g. Y at the second position, Z at the third, and so on). The resulting swizzle will behave like the identity when used in any instruction with the original writemask. I've manually verified that *none* of the callers of both conversion constructors were relying on the previous broken semantics. There are no piglit regressions on any generation. Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Pass argument by reference to src_reg/dst_reg conversion ↵Francisco Jerez2015-03-232-4/+4
| | | | | | constructors. Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Remove swizzle_for_size() in favour of brw_swizzle_for_size().Francisco Jerez2015-03-233-31/+8
| | | | | | | | | | It could be objected that swizzle_for_size() is "faster" than brw_swizzle_for_size(). It's not measurably better in any reasonable CPU-bound benchmark on VLV according to the Finnish benchmarking system (including the SynMark2 DrvShComp shader compilation benchmark). Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Remove broken vector size deduction in ↵Francisco Jerez2015-03-231-14/+9
| | | | | | | | | | | setup_builtin_uniform_values(). This seemed to be trying to deduce the number of uniform vector components from the parameter swizzle, but the algorithm would always give 4 as result. Instead grab the correct number of components from the GLSL type. Reviewed-by: Matt Turner <[email protected]>
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