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* i965: Share OPCODE_TXB between brw_wm_emit.c and brw_wm_glsl.cEric Anholt2009-11-133-101/+63
* i965: Share OPCODE_TEX between brw_wm_emit.c and brw_wm_glsl.c.Eric Anholt2009-11-133-118/+72
* i965: Clean up emit_tex a bit.Eric Anholt2009-11-131-27/+24
* Merge remote branch 'origin/mesa_7_6_branch'Eric Anholt2009-11-1310-46/+81
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| * i965: Fix Ironlake shadow comparisons.Eric Anholt2009-11-121-7/+17
| * i965: Fix VBO last-valid-offset setup on Ironlake.Eric Anholt2009-11-121-10/+3
| * i965: fix EXT_provoking_vertex supportRoland Scheidegger2009-11-118-29/+61
* | i965: Flag BRW_NEW_CONTEXT on some context state.Eric Anholt2009-11-132-6/+6
* | intel: Remove some dead context structure fields.Eric Anholt2009-11-131-2/+0
* | i965: Remove an unused cache_item field.Eric Anholt2009-11-133-3/+1
* | i965: Remove long dead structures for ffvertex_prog.c.Eric Anholt2009-11-131-17/+0
* | i965: Use bo_map instead of subdata to upload the bits of constant buffer.Eric Anholt2009-11-132-2/+26
* | i965: Validate the number of URB entries selected for the VS.Eric Anholt2009-11-131-4/+33
* | intel: When subdataing a busy buffer, use a temporary and blit in.Eric Anholt2009-11-131-3/+16
* | i965: Clean up Ironlake sampler type definitions.Eric Anholt2009-11-133-18/+10
* | i965: Avoid moving the current value back into the accumulator for MAD.Eric Anholt2009-11-131-1/+34
* | intel: Don't check for context pointer to be NULL during extension initIan Romanick2009-11-121-7/+6
* | intel: Remove unused enable_imaging parameter to intelInitExtensionsIan Romanick2009-11-123-6/+4
* | r300, r300g: Add missing registers.Corbin Simpson2009-11-111-0/+2
* | Merge remote branch 'origin/mesa_7_6_branch'Eric Anholt2009-11-101-1/+11
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| * i965: Fix VS constant buffer value loading.Eric Anholt2009-11-101-1/+11
| * i965: Unalias src/dst registers for SGE and friends.Eric Anholt2009-11-101-19/+21
| * i965: Allow use of PROGRAM_LOCAL constants in ARB_vp.Eric Anholt2009-11-101-1/+1
| * r600: don't emit htile regsAlex Deucher2009-11-091-4/+2
* | i965: avoid memsetting all the BRW_WM_MAX_INSN arrays for every compile.Eric Anholt2009-11-104-4/+23
* | i965: Add a note explaining the data cache domain.Eric Anholt2009-11-101-1/+4
* | i965: Unalias src/dst registers for SGE and friends.Eric Anholt2009-11-101-19/+21
* | i965: Allow use of PROGRAM_LOCAL constants in ARB_vp.Eric Anholt2009-11-101-1/+1
* | r600/r700: typo, fix mask of DB_ALPHA_TO_MASKJerome Glisse2009-11-091-3/+3
* | r600: rework DB render setupAlex Deucher2009-11-094-42/+73
* | r600: don't emit htile regsAlex Deucher2009-11-091-4/+2
* | r600: add missing ZPASS setup bits for r7xx+Alex Deucher2009-11-092-0/+6
* | i965: Use Compr4 instruction compression mode on G4X and newer.Eric Anholt2009-11-063-17/+29
* | i965: Share min/max between brw_wm_emit.c and brw_wm_glsl.cEric Anholt2009-11-063-60/+72
* | i965: Share emit_fb_write() between brw_wm_emit.c and brw_wm_glsl.cEric Anholt2009-11-064-127/+40
* | i965: Share most of the WM functions between brw_wm_glsl.c and brw_wm_emit.cEric Anholt2009-11-063-297/+109
* | i965: Share math functions between brw_wm_glsl.c and brw_wm_emit.c.Eric Anholt2009-11-063-221/+111
* | i965: Share the sop opcodes between brw_wm_glsl.c and brw_wm_emit.c.Eric Anholt2009-11-063-74/+29
* | i965: Share OPCODE_MAD between brw_wm_glsl.c and brw_wm_emit.cEric Anholt2009-11-063-30/+13
* | i965: Share the DP3, DP4, and DPH between brw_wm_glsl.c and brw_wm_emit.cEric Anholt2009-11-063-99/+33
* | i965: Add generic GLSL code for unaliasing a 3-arg opcode, and share LRP code.Eric Anholt2009-11-063-45/+71
* | i965: Use a normal alu1 emit for OPCODE_TRUNC.Eric Anholt2009-11-062-34/+2
* | i965: Share basic ALU ops between brw_wm_glsl and brw_wm_emit.cEric Anholt2009-11-063-117/+38
* | i965: Collect GLSL src/dst regs up in generic code.Eric Anholt2009-11-062-7/+17
* | intel: better front color buffer test in intelClear()Brian Paul2009-11-061-2/+3
* | i965: Always pass the size argument to brw_cache_data.Eric Anholt2009-11-066-57/+21
* | intel: Finish removing the fallback code for bug #16697.Eric Anholt2009-11-061-6/+2
* | intel: Don't validate in a texture image used as a render target.Eric Anholt2009-11-063-11/+15
* | intel: Clean up some extra struct indirection in finalize.Eric Anholt2009-11-061-2/+1
* | intel: Use _mesa_get_current_tex_object() to clean up TFP path.Eric Anholt2009-11-061-4/+4
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