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* Merge git://proxy01.pd.intel.com:9419/git/mesa/mesa into crestlineNian Wu2007-03-169-114/+119
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| * r300: Added _mesa_copy_instructions.Oliver McFadden2007-03-152-5/+6
| * r300: Renamed r300_vertexprog.c to r300_vertprog.cOliver McFadden2007-03-152-1/+1
| * r300: Use _mesa_alloc_instructions/_mesa_init_instructions instead of malloc.Oliver McFadden2007-03-152-14/+11
| * r300: Updated R300 to use the new SWIZZLE macros.Oliver McFadden2007-03-152-9/+9
| * r300: Fixed an unused variable warning and removed some cruft, too.Oliver McFadden2007-03-151-26/+0
| * r300: Fixed a printf conversion warning.Oliver McFadden2007-03-151-2/+2
| * r300: Fixed "no previous prototype for 'r300RefillCurrentDmaRegion'" warning.Oliver McFadden2007-03-151-2/+2
| * Committed Rune Petersen's fragment.position patch (Bug #10024) plus a few smallOliver McFadden2007-03-154-70/+103
| * Fix off by one error in immediate state packet size.Keith Whitwell2007-03-151-1/+1
* | Merge git://proxy01.pd.intel.com:9419/git/mesa/mesa into crestlineNian Wu2007-03-152-6/+9
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| * clear the b->frontxrb->drawable field in xmesa_free_buffer(), see bug 7205Brian2007-03-141-0/+6
| * Merge branch 'master' of git+ssh://[email protected]/git/mesa/mesaBrian2007-03-1415-29/+54
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| * | move CLIENT_ID code in xmesa_delete_framebuffer(), see bug 7205Brian2007-03-141-6/+3
* | | Merge git://proxy01.pd.intel.com:9419/git/mesa/mesa into crestlineNian Wu2007-03-1413-26/+39
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| * | sync up t_vp_build.c brw_vs_tnl.c a bitRoland Scheidegger2007-03-131-15/+12
| * | enable ARB_vertex_buffer_object for more dri driversRoland Scheidegger2007-03-138-0/+16
| * | r300: Renamed the CACHE_CTLSTAT values to include UNKNOWN in the name; notOliver McFadden2007-03-134-11/+11
* | | Merge git://proxy01.pd.intel.com:9419/git/mesa/mesa into crestlineNian Wu2007-03-1313-41/+59
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| * | Add defines for the values written to R300_RB3D_ZCACHE_CTLSTAT.Oliver McFadden2007-03-133-3/+5
| * | Documented the value written for R300_TX_CNTL cache flush.Oliver McFadden2007-03-132-1/+3
| * | Corrected values written to R300_RB3D_DSTCACHE_CTLSTAT to eitherOliver McFadden2007-03-133-4/+4
| * | Guess another unknown register used for R300 pacification.Oliver McFadden2007-03-133-3/+7
| * | i915tex: Don't crash when intel_fb->color_rb[i] is NULL.Michel Dänzer2007-03-121-1/+5
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| * r200: Simplify r200SetCliprects like radeonSetCliprects in radeon and r300.Alan Swanson2007-03-124-22/+22
| * r200: Adapt cliprect fixes from r300.Alan Swanson2007-03-123-3/+6
| * radeon: Adapt cliprect fixes from r300.Alan Swanson2007-03-123-5/+8
* | Merge git://proxy01.pd.intel.com:9419/git/mesa/mesa into crestlineNian Wu2007-03-1224-406/+766
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| * fix for bug#10196Xiang, Haihao2007-03-111-1/+8
| * Guess another unknown register in R300 command buffer initialization. (Oliver...Aapo Tahkola2007-03-114-5/+6
| * Renamed some of the unkXXX variables in the command buffer initOliver McFadden2007-03-113-72/+73
| * i915tex: Fix build against libdrm git...Michel Dänzer2007-03-102-2/+3
| * i915tex: Fix intel_wait_flips being declared implicitly.Michel Dänzer2007-03-101-0/+1
| * i915tex: Fix build against released version of libdrm.Michel Dänzer2007-03-101-0/+17
| * nouveau: fix nv04 swtcl.Stephane Marchesin2007-03-101-0/+1
| * nouveau: fix the nv04 swtcl code.Stephane Marchesin2007-03-101-1/+1
| * nouveau: oops don't debug by default.Stephane Marchesin2007-03-101-1/+1
| * nouveau: some fixes to the nv04 state code.Stephane Marchesin2007-03-101-13/+15
| * nouveau: add a fifo size debug check.Stephane Marchesin2007-03-102-3/+23
| * Merge branch 'i915tex-pageflip'Michel Dänzer2007-03-1012-304/+608
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| | * i915tex: Wait for pending scheduled flips before switching vsync pipe.Michel Dänzer2007-03-091-0/+19
| | * i915tex: Set intel_fb->vbl_waited to current instead of what we aimed for.Michel Dänzer2007-03-091-1/+1
| | * i915tex: Sync pages between pipes immediately again.Michel Dänzer2007-03-091-2/+12
| | * i915tex: Do not wait for pending flips on both pipes at the same time.Michel Dänzer2007-03-091-9/+4
| | * i915tex: Set framebuffer size to match window before calling _mesa_make_current.Michel Dänzer2007-03-071-10/+10
| | * i915tex: Sync pages differently when crossing pipe borders.Michel Dänzer2007-02-281-12/+18
| | * i915tex: Check that intel_rb is valid before trying to add it to an fbo.Michel Dänzer2007-02-281-2/+4
| | * i915tex: Also update intel_rb->vbl_pending when scheduled swap is not a flip.Michel Dänzer2007-02-281-3/+3
| | * i915tex: Schedule flips when possible.Michel Dänzer2007-02-226-179/+228
| | * i915tex: Triple buffering support, only effective with page flipping so far.Michel Dänzer2007-02-207-63/+166
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