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* intel: Require the right amount of space in glBitmap blit acceleration.Pierre Willenbrock2008-12-081-1/+1
| | | | | This leads to problems when the batchbuffer is flushed, but the bitmap data could not fit into it.
* intel: Fall back on rendering to a texture attachment with a border.Eric Anholt2008-12-061-1/+8
| | | | Fixes a segfault in oglconform fbo.c test.
* intel: Fix crash in automatic mipmap generation for glCopyTex{Sub,}Image.Eric Anholt2008-12-061-1/+1
| | | | | | The images aren't mapped at this point, so we want the generic Mesa path for GenerateMipmapEXT that does the mapping/unmapping for us. Ideally Mesa would just call it for us.
* intel: Fix glCopyPixels blit acceleration for FBO destinations.Eric Anholt2008-12-061-48/+56
| | | | | This was another opportunity to either get clipped to screen size or not get clipped enough and draw outside of object boundaries.
* intel: Fix glBitmap blit acceleration for FBO destinations.Eric Anholt2008-12-061-33/+39
| | | | | Bug #18914. Fixes fbo_firecube hang due to drawing outside the FBO bounds. Thanks to Pierre Willenbrock for debugging the issue.
* intel: Put CopyTexImage fallback under DEBUG_FALLBACKS not DEBUG_TEXTURE.Eric Anholt2008-12-061-1/+3
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* i965: Fix failure to upload new constant data when changing programs.Eric Anholt2008-12-034-10/+2
| | | | | | | | | | | | This is fallout from the ffvertex_prog.c work. It doesn't call ProgramStringNotify, so we don't set param_state, so we wouldn't track when VP parameters changed, and constants wouldn't get uploaded. Instead, remove param_state entirely and just use the real value that we want to be tracking. Fixes rendering in openarena since BRW_NEW_BATCH got disentangled from BRW_NEW_INDICES. Bug #18822.
* i965: Fix stray character that the compile whined about.Eric Anholt2008-12-031-0/+0
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* intel: restore old vertex submit paths for i8xx hardware.Dave Airlie2008-12-026-6/+124
| | | | | | | Intel docs state that only 830/845 have VBOs, 855/865 don't. So lets just not use them on i8xx at all. This restores the old pre-vbo code and uses it on all 8xx hw.
* i965: Add a new state flag BRW_NEW_NR_SURFACES instead of CACHE_NEW_SURFACEEric Anholt2008-11-283-4/+10
| | | | | | The CACHE_NEW_SURFACE bit always gets spammed since we get many different surface BOs per state emit, but the only consumer of it wanted to just know how many surfaces were enabled.
* i965: Fix clashing enums for BRW_NEW_INDICES/VERTICES versus BATCH/DEPTH_BUFFER.Eric Anholt2008-11-281-4/+4
| | | | Fixes upload of large amounts of state for every new primitive emit.
* i965: Remove BRW_WM_LOCK dirty bit, introduced to work around lack of relocs.Eric Anholt2008-11-284-6/+1
| | | | This was causing a prepare of wm state at every primitive emit.
* i965: Add debug code for dumping how frequently different dirty bits are set.Eric Anholt2008-11-281-0/+126
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* i915: Remove dead early z enable bit which was always on.Eric Anholt2008-11-283-66/+1
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* i965: Reduce fast-pathiness of brw_try_draw_prims, bringing in important checks.Eric Anholt2008-11-281-51/+52
| | | | | | | Later primitives, even if they caused a full state validate, wouldn't check that there was enough space in the batchbuffer, occasionally triggering the sanity check. We also skipped the aperture space check, even if it would mean bringing in new programs and associated state.
* windows: fix visual object memleakThomas Henn2008-11-261-0/+3
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* windows: fix _mesa_unreference_framebuffer() to pass ** type.Thomas Henn2008-11-261-1/+3
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* windows: replace free() with _mesa_unreference_framebuffer()Brian Paul2008-11-241-1/+1
| | | | Fixes invalid memory reference bug when exiting.
* i965: Add support for accelerated CopyTexSubImage.Eric Anholt2008-11-213-68/+41
| | | | | | | | | | | There were hacks in EmitCopyBlit before to adjust offsets so that y=0 after the offsets had been adjusted for a negative pitch. It appears that those hacks were due to an unclear and surprising aspect of the hardware: inverting the pitch results in the blit into the specified rectangle being inverted, without the user needing to adjust y and base offset. Tested with piglit copytexsubimage test on 915GM and GM965. Should fix serious performance issues with ETQW and other applications.
* intel: Don't glBitmap fallback with scissoring enabled.Eric Anholt2008-11-211-6/+0
| | | | | The blit bitmap code already handles scissoring. This is a 15-100% speedup on blender benchmark.blend thanks to avoiding fallbacks. Bug #17951.
* i915: Don't overwrite i915's Viewport function from generic code.Eric Anholt2008-11-214-3/+12
| | | | Instead, have i965 and i915 both call the generic function from their Viewport.
* intel: fix i830 comment + backwards VB offsets.airlied2008-11-202-3/+3
| | | | According to Keith the docs have these offsets the other way around
* intel: fix i8xx vbo enable bitairlied2008-11-201-1/+1
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* intel: add lots of i830 engine to intel_decode debugairlied2008-11-201-20/+110
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* i965: Upload state on primitive switch, don't just prepare it.Eric Anholt2008-11-121-0/+1
| | | | | This was a regression in 59b2c2adbbece27ccf54e58b598ea29cb3a5aa85 that broke blender, among other apps.
* i965: Fix VB refcount leak on aperture overflow.Eric Anholt2008-11-121-0/+1
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* i965: Fix up VS max_threads for G4X and removing a magic number.Eric Anholt2008-11-121-2/+14
| | | | | | As far as I can read in the docs, VS threads can be 1:1 with the pairs of VUE handles allocated for them. Also, G4X can run twice as many threads as before (though we won't unless the we bump the preferred URB entries for VS).
* i965: Fix up SF max_threads.Eric Anholt2008-11-121-1/+2
| | | | | | We were dividing the number of URB entries by two to get number of threads, which looks suspiciously like a copy'n'paste-o from brw_vs_state.c. Also, the maximum number of threads is 24, not 12.
* i965: Fix up clip min_nr_entries, preferred_nr_entries, and max_threads.Eric Anholt2008-11-122-2/+16
| | | | | | | | | The clip thread could potentially deadlock when processing tristrips since being moved back to dual-thread mode, as the two threads could each have 4 VUEs referenced and not be able to allocate another one since SF processing wasn't able to continue (needing 5 entries before it freed 2). In constrained URB mode, similar deadlock could even have occurred with polygons (so we cut back max_threads if we can't handle it any primitive type).
* i965: Update WM maximum threads for G4X.Eric Anholt2008-11-121-2/+7
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* i965: Add a big comment explaining my understanding of URB management.Eric Anholt2008-11-121-1/+38
| | | | | It shouldn't offer anything new over what's in the docs (except for G4X notes), but here it's all in one place.
* intel: reset cliprect_mode to IGNORE_CLIPRECTS.Xiang, Haihao2008-11-111-1/+3
| | | | | | This ensures all batchbuffers have a same cliprect mode after calling _intel_batchbuffer_flush even if there aren't invalid commands in the current batch buffer. (fix bug#18362).
* mesa: restore glapi/ prefix on #includeBrian Paul2008-11-101-1/+1
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* GLX: fix out-of-bounds memory issue in indirect glAreTexturesResident()Brian Paul2008-11-101-17/+17
| | | | | | | | | | | | | | | | See bug 18445. When getting array results, __glXReadReply() always reads a multiple of four bytes. This can cause writing to invalid memory when 'n' is not a multiple of four. Special-case the glAreTexturesResident() functions now. To fix the bug, we use a temporary buffer that's a multiple of four bytes in length. NOTE: this commit also reverts part of commit 919ec22ecf72aa163e1b97d8c7381002131ed32c (glx/x11: Added some #ifdef GLX_DIRECT_RENDERING protection) which directly edited the indirect.c file rather than the python generator! I'm not repairing that issue at this time.
* dri: alloc __DRIscreen object with calloc()Brian Paul2008-11-101-1/+1
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* mesa: rename OPCODE_INT -> OPCODE_TRUNCBrian Paul2008-11-061-4/+4
| | | | Trunc is a more accurate description; there's no type conversion involved.
* i965: Always check vertex program.Xiang, Haihao2008-11-061-1/+4
| | | | | | Now i965 also uses the vertex program created by Mesa Core, but this vertex program is not only depend on mesa state _NEW_PROGRAM, so always check the current vertex program is updated or not. This fixes broken demo cubemap.
* i965: Implement missing OPCODE_NOISE3 instruction in fragment shaders.Gary Wong2008-11-052-10/+335
| | | | OPCODE_NOISE4 coming later.
* i965: Clean up stale NDC comment.Eric Anholt2008-11-021-2/+1
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* i965: Avoid vs header computation for negative rhw on G4X.Eric Anholt2008-11-021-3/+3
| | | | This cuts one MOV out when setting a zero header.
* i965: Merge GM45 into the G4X chipset define.Eric Anholt2008-11-029-25/+24
| | | | | The mobile and desktop chipsets are the same, and having them separate is more typing and more chances to screw up.
* i965: Fix copy'n'paste issue that made brw->urb.constrained useless.Eric Anholt2008-11-021-3/+7
| | | | Also, add a comment explaining what brw->urb.constrained tries to do.
* Fix for 58dc8b7: dest regions must not use HorzStride 0 in ExecSize 1Keith Packard2008-11-011-0/+4
| | | | | | | | | | | | | | | | | | | | | | | Quoting section 11.3.10, paragraph 10.2 of the 965PRM: 10.2. If ExecSize is 1, dst.HorzStride must not be 0. Note that this is relaxed from rule 10.1.2. Also note that this rule for destination horizontal stride is different from that for source as stated in rule #7. GM45 gets very angry when rule 10.2 is violated. Patch 58dc8b7 (i965: support destination horiz strides in align1 access mode) added support for additional horizontal strides in the ExecSize 1 case, but failed to notice that mesa occasionally re-purposes a register as a temporary destination, even though it was constructed as a repeating source with HorzStride = 0. While, ideally, we should probably fix the code using these register specifications, this patch simply rewrites them to use HorzStride 1 as the pre-58dc8b7 code did. Signed-off-by: Keith Packard <[email protected]>
* intel: pixelzoom doesn't apply to glBitmap, so disable the fallback.Eric Anholt2008-10-311-5/+1
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* intel: Remove fallback for glDrawPixels(GL_COLOR_INDEX)Eric Anholt2008-10-311-7/+0
| | | | | GL_COLOR_INDEX mode is just like other normal formats (that is, not depth/stencil) and is uploaded fine by TexImage.
* intel: Add more fallback debugging for glDrawPixels.Eric Anholt2008-10-311-8/+33
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* i965: implement the missing OPCODE_NOISE1 and OPCODE_NOISE2 instructions.Gary Wong2008-10-312-3/+405
| | | | (Only in fragment shaders, so far. Support for NOISE3 and NOISE4 to come.)
* i965: support destination horiz strides in align1 access mode.Gary Wong2008-10-312-3/+3
| | | | This is required for scatter writes in destination regions to work.
* intel: Fix glDrawPixels with 4d RasterPos.Eric Anholt2008-10-281-4/+9
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* i965: Fix check_aperture calls to cover everything needed for the prim at once.Eric Anholt2008-10-289-81/+133
| | | | | | | | Previously, since my check_aperture API change, we would check each piece of state against the batchbuffer individually, but not all the state against the batchbuffer at once. In addition to not being terribly useful in assuring success, it probably also increased CPU load by calling check_aperture many times per primitive.
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