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* i915: replace __FUNCTION__ with __func__Marius Predut2015-04-1424-107/+107
| | | | | | | | Consistently just use C99's __func__ everywhere. No functional changes. Acked-by: Matt Turner <[email protected]> Signed-off-by: Marius Predut <[email protected]>
* swrast: replace __FUNCTION__ with __func__Marius Predut2015-04-142-3/+3
| | | | | | | | | | | Consistently just use C99's __func__ everywhere. The patch was verified with Microsoft Visual studio 2013 redistributable package(RTM version number: 18.0.21005.1) Next MSVC versions intends to support __func__. No functional changes. Acked-by: Matt Turner <[email protected]> Signed-off-by: Marius Predut <[email protected]>
* i965/fs: Correct mistake in determining whether a MUL is negated.Matt Turner2015-04-141-1/+1
| | | | | | | | | a * b is equivalent to -a * -b, and the previous code was failing at that. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89961 Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/skl: Use an exec size of 8 to initialise the message headerNeil Roberts2015-04-142-2/+2
| | | | | | | | | | | | | | | | | | Commit e93566a15c61c33faa changed the message header code needed to make Skylake use SIMD4x2 so that it uses a register with width 4 instead of 8 as the source register in the send message. However it also changed the width for the dest in the MOV instruction which is used to initialise the header register with the values from g0. The width of the destination is used to determine the exec size in brw_set_dest so this would end up making the MOV have an exec size of 4. I think this would end up leaving the top half of the register uninitialised. The top half of the header has meaningful values so this probably isn't a good idea. This patch just casts the dest register for the MOV instruction back to a vec8 to fix it. It doesn't cause any changes to a Piglit run. Reviewed-by: Ben Widawsky <[email protected]>
* i965/fs: Always invert predicate of SEL with swapped argumentsIan Romanick2015-04-141-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | Commit b616164 added an optimization of b2f generation of a comparison. It also included an extra optimization of one of the comparison values is a constant of zero. The trick was that some value was known to be zero, so that value could be used in the SEL instruction instead of potentially loading 0.0 into a register. This change switched the order of the arguments to the SEL, and, for some unknown reason, I thought that the predicate should therefore only be inverted for the == case. Clearly, it should always be inverted. Fixes piglit fs-notEqual-of-expression.shader_test and fs-equal-of-expression.shader_test. v2: Don't do the "register already has zero" optimization for the '== 0' case. In that case, the register does not have zero when we want to produce a zero result. Signed-off-by: Ian Romanick <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89722 Reviewed-by: Kenneth Graunke <[email protected]> [v1] Tested-by: Lu Hua <[email protected]>
* i965: Implement proper workaround for Gen4 GPU CONSTANT_BUFFER hangs.Kenneth Graunke2015-04-141-13/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | I finally managed to dig up some information on our mysterious GPU hangs. A wiki page from the Crestline validation team mentions that they found a GPU hang in "Serious Sam 2" (on Windows) with remarkably similar conditions to the ones we've seen in Google Chrome and glmark2. Apparently, if WM_STATE has "PS Use Source Depth" enabled, CC_STATE has most depth state disabled, and you issue a CONSTANT_BUFFER command and immediately draw, the depth interpolator makes a small mistake that leads to hangs. Most of the traces I looked at contained a CONSTANT_BUFFER packet immediately followed by 3DPRIMITIVE, or at least very few packets. It appears they also have "PS Use Source Depth" enabled - either at the hang, or a little before it. So I think this is our bug. The workaround is to emit a non-pipelined state packet after issuing a CONSTANT_BUFFER packet. This is really similar to the workaround I developed in commit c4fd0c9052dd391d6f2e9bb8e6da209dfc7ef35b. v2: Fix word-wrapping issues. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Francisco Jerez <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Fix INTEL_DEBUG=shader_time for SIMD8 VS.Kenneth Graunke2015-04-141-0/+3
| | | | | | | | | In commit 4ebeb71573ad44f7657810dc5dd2c9030e3e63db, I deleted the emit_shader_time_end() call in emit_urb_writes(). But I failed to add it to run_vs(), as I intended. So no data was recorded at all. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Flush batchbuffer containing the query on glQueryCounter.Mathias Froehlich2015-04-131-0/+2
| | | | | | | | | | | | | This change fixes a regression with timer queries introduced with commit 3eb6258. There the pending batchbuffer is flushed only if glEndQuery is executed. This present change adds such a flush to glQueryCounter which also schedules a value query just like glEndQuery does. The patch fixes GPU timer queries going mad from within osgviewer. Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Mathias Froehlich <[email protected]> Cc: [email protected]
* i965: Don't bother freeing NULL.Matt Turner2015-04-131-4/+2
| | | | | | | Commit e16c5c90 was replacing 'region' with 'mt', leaving this nonsensical code. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Lift some restrictions on dma_buf EGLImagesChad Versace2015-04-133-22/+7
| | | | | | | | | | | | | | | | | | | | | Allow glEGLImageTargetRenderbufferStorageOES and glEGLImageTargetTexture2DOES for dma_buf EGLImages if the image is a single RGBA8 unorm plane. This is safe, despite fast color clears, because i965 disables allocation of auxiliary buffers for EGLImages. Chrome OS needs this, because its compositor uses dma_buf EGLImages for its scanout buffers. Testing: - Tested on Ivybridge Chromebook Pixel with WebGL Aquarium and YouTube. - No Piglit regressions on Broadwell with `piglit run -p gbm tests/quick.py`, with my Piglit patches that update the EGL_EXT_image_dma_buf_import tests. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Disable aux buffers for EGLImage-backed miptreesChad Versace2015-04-132-5/+19
| | | | | | | | | | | | | | | | | | | | EGL does not yet have extensions to manage the flushing and invalidating of driver-internal aux buffers. So we must disable aux buffers of dma_buf-backed EGLImages in order to safely render into them. This patch is obviously needed for renderbufers. It's also needed for textures because the user can attach the texture to a framebuffer and because the driver sometimes renders to textures for internal reasons. Testing: - Tested on Ivybridge Chromebook Pixel with WebGL Aquarium and YouTube. - No Piglit regressions on Broadwell with `piglit run -p gbm tests/quick.py`. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Change intel_miptree_create_for_bo() signatureChad Versace2015-04-136-11/+21
| | | | | | | | | | | Add parameter 'bool disable_aux_buffers'. This is a refactor patch. The patch changes no behavior because the new parameter is false in every call. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Add field intel_mipmap_tree::disable_aux_buffersChad Versace2015-04-132-2/+29
| | | | | | | | | | | | | | | | | | | | | | The new field disables allocation of auxiliary buffers, such as the HiZ buffer and MCS buffer. This is useful for sharing the miptree bo with an external client that doesn't understand auxiliary buffers. We need this field to safely render to a buffer that was imported with EGL_EXT_image_dma_buf_import, because EGL does not yet have extensions to manage flushing and invalidating auxiliary buffers. Nothing yet enables this field. That's left to follow-up patches. Testing: - Tested on Ivybridge Chromebook Pixel with WebGL Aquarium and YouTube. - No Piglit regressions on Broadwell with `piglit run -p gbm tests/quick.py`. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Refactor brw_is_hiz_depth_format()Chad Versace2015-04-135-25/+30
| | | | | | | | | | | | | | | | | | | | | Every caller of this function uses it to determine if the current miptree needs a hiz buffer to be allocated. Strangely, the function doesn't take a miptree argument. So, this function effectively decides if and when a miptree's hiz buffer gets allocated without inspecting the miptree itself. Luckily, the driver behaves correctly despite the brw_is_hiz_depth_format's quirk. I will soon make some changes to the miptree that will require inspecting the miptree to determine if it needs a hiz buffer. So this patch renames brw_is_hiz_depth_format -> intel_miptree_wants_hiz_buffer and gives it a miptree parameter. This patch shouldn't change any behavior. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Declare intel_miptree_create_layout() as staticChad Versace2015-04-132-14/+1
| | | | | | | | It's not used outside intel_mipmap_tree.c. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Declare intel_miptree_alloc_mcs() as staticChad Versace2015-04-132-6/+6
| | | | | | | | It's not used outside of intel_mipmap_tree.c, nor should it ever be. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/nir: Make INTEL_DEBUG=ann work with NIR.Kenneth Graunke2015-04-112-1/+8
| | | | | | | | | Now that we store a copy of the NIR shader, and don't immediately free it, we can use it in annotations as well. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Create NIR during LinkShader() and ProgramStringNotify().Kenneth Graunke2015-04-117-176/+250
| | | | | | | | | | | | | | | | | | | | | | | Previously, we translated into NIR and did all the optimizations and lowering as part of running fs_visitor. This meant that we did all of that work twice for fragment shaders - once for SIMD8, and again for SIMD16. We also had to redo it every time we hit a state based recompile. We now generate NIR once at link time. ARB programs don't have linking, so we instead generate it at ProgramStringNotify time. Mesa's fixed function vertex program handling doesn't bother to inform the driver about new programs at all (which is rather mean), so we generate NIR at the last minute, if it hasn't happened already. shader-db runs ~9.4% faster on my i7-5600U, with a release build. v2: Check NirOptions != NULL in ProgramStringNotify(). Don't bother using _mesa_program_enum_to_shader_stage as we already know it. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir: Store num_direct_uniforms in the nir_shader.Kenneth Graunke2015-04-111-2/+3
| | | | | | | | | | | | | | Storing this here is pretty sketchy - I don't know if any driver other than i965 will want to use it. But this will make it a lot easier to generate NIR code at link time. We'll probably rework it anyway. (Ian suggested making nir_assign_var_locations_scalar_direct_first simply modify the nir_shader's fields, rather than passing pointers to them. If this stays long term, we should do that. But Jason and I suspect we'll be reworking this area again in the near future.) Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Move lower_output_reads to brw_link_shader().Kenneth Graunke2015-04-112-1/+3
| | | | | | | | This makes it so emit_nir_code() doesn't modify the GLSL IR. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Remove useless null check.Matt Turner2015-04-111-4/+0
| | | | If it were null, we'd have just derefernced it two lines above.
* i965/fs/nir: Mark fallthrough.Matt Turner2015-04-111-0/+2
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* i965: Remove useless reg_offset >= 0 tests.Matt Turner2015-04-112-2/+0
| | | | Commit eb9bd3a1 changed the type of this field to uint16_t.
* nir: split out lower_sub from lower_negateRob Clark2015-04-111-0/+1
| | | | | | | | | | Originally you had to have one or the other. But actually I don't want either. (Or rather I want whatever is the minimum # of instructions.) TODO: not sure where the best place to insert a check that driver hasn't set *both* lower_negate and lower_sub? Signed-off-by: Rob Clark <[email protected]>
* i965: Use NIR by default for fragment shadersJason Ekstrand2015-04-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GLSL IR vs. NIR shader-db results on i965: total instructions in shared programs: 2889747 -> 2890782 (0.04%) instructions in affected programs: 2425446 -> 2426481 (0.04%) helped: 3698 HURT: 5341 GLSL IR vs. NIR shader-db results on g4x: total instructions in shared programs: 2547252 -> 2550440 (0.13%) instructions in affected programs: 1984482 -> 1987670 (0.16%) helped: 2844 HURT: 4776 GLSL IR vs. NIR shader-db results on Iron Lake: total instructions in shared programs: 4053381 -> 4063828 (0.26%) instructions in affected programs: 3026601 -> 3037048 (0.35%) helped: 4110 HURT: 8331 GAINED: 1287 LOST: 9 GLSL IR vs. NIR shader-db results on Sandy Bridge: total instructions in shared programs: 5307041 -> 5236666 (-1.33%) instructions in affected programs: 3442908 -> 3372533 (-2.04%) helped: 11829 HURT: 5604 GAINED: 33 LOST: 18 GLSL IR vs. NIR shader-db results on Ivy Bridge: total instructions in shared programs: 4926333 -> 4857017 (-1.41%) instructions in affected programs: 3144042 -> 3074726 (-2.20%) helped: 11559 HURT: 4774 GAINED: 46 LOST: 25 GLSL IR vs. NIR shader-db results on Bay Trail: total instructions in shared programs: 4926333 -> 4857017 (-1.41%) instructions in affected programs: 3144042 -> 3074726 (-2.20%) helped: 11559 HURT: 4774 GAINED: 46 LOST: 25 GLSL IR vs. NIR shader-db results on Haswell: total instructions in shared programs: 4392487 -> 4293476 (-2.25%) instructions in affected programs: 2800180 -> 2701169 (-3.54%) helped: 13073 HURT: 3383 GAINED: 46 LOST: 23 GLSL IR vs. NIR shader-db results on Broadwell (FS only): total instructions in shared programs: 4378113 -> 4283025 (-2.17%) instructions in affected programs: 2743209 -> 2648121 (-3.47%) helped: 12470 HURT: 3609 GAINED: 64 LOST: 27 Signed-off-by: Jason Ekstrand <[email protected]> Acked-by: Matt Turner <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Don't set NirOptions for stages that will use the vec4 backend.cros-mesa-10.6-vanillachadv/cros-mesa-10.6-vanillachadv/cros-gerrit-262788-baseKenneth Graunke2015-04-101-9/+6
| | | | | | | | | | | | | | | | | | | We've started using NirOptions != NULL to mean "we're using NIR for this stage." However, when INTEL_USE_NIR=1, we set it for a bunch of stages that still use the vec4 backend, and thus definitely aren't using NIR. For example, if INTEL_USE_NIR=1 we disable the GLSL IR cubemap normalization pass, even for vertex shaders and geometry shaders. This is wrong, but breaks a very uncommon case. When I started deleting GLSL IR for stages where we claimed to be using NIR, this bug quickly became apparent. For now, only set it for fragment shaders, and vertex shaders if brw->scalar_vs is set. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/disasm: Print the type after the swizzle also for 3src src operandsVille Syrjälä2015-04-101-3/+3
| | | | | | | | | The disassembly currently has the swizzle after the type for 3src source operands, and the other way around for 2src. Flip the type and swizzle around for 3src so that the output matches 2src. Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]>
* i965: Move brw_link_shader's GLSL IR transformations into a helper.Kenneth Graunke2015-04-101-93/+99
| | | | | | | | This function was getting a bit large and unwieldy. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Change brw_shader to gl_shader in brw_link_shader().Kenneth Graunke2015-04-101-32/+31
| | | | | | | | | Nothing actually wanted brw_shader fields - we just had to type shader->base all over the place for no reason. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* nir: Make nir_lower_samplers take a gl_shader_stage, not a gl_program *.Kenneth Graunke2015-04-101-1/+1
| | | | | | | | | | We don't actually need a gl_program struct. We only used it to translate prog->Target (i.e. GL_VERTEX_PROGRAM) to the gl_shader_stage (i.e. MESA_SHADER_VERTEX). We may as well just pass that. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/skl: Fix the order of the arguments for the LD sampler messageNeil Roberts2015-04-081-2/+13
| | | | | | | | | | | | | | In Skylake the order of the arguments for sample messages with the LD type are u, v, lod, r whereas previously they were u, lod, v, r. This fixes 144 Piglit tests including ones that directly use texelFetch and also some using the meta stencil blit path which appears to use texelFetch in its shader. v2: Fix sampling 1D textures Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965: Fix depth field setting in surface state for raw buffer on Gen7/8Zhenyu Wang2015-04-082-4/+10
| | | | | | | | | | On Gen7/8 for RAW surface format, the depth field (surf[3]) in surface state means [30:21] bits of number of entries which is different from other surface format which uses [26:21] bits field. Signed-off-by: Zhenyu Wang <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965: Add the ability to render to I8/L8 and I16/L16 UNORM formats.Kenneth Graunke2015-04-071-0/+8
| | | | | | | | This allows those formats to work with the meta PBO upload path. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965: Use SET_FIELD in 3DSTATE_STREAMOUT packets.Kenneth Graunke2015-04-072-16/+16
| | | | | | | | Suggested by Topi Pohjolainen. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965: Do not render primitives in non-zero streams then TF is disabledIago Toral Quiroga2015-04-061-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Haswell hardware seems to ignore Render Stream Select bits from 3DSTATE_STREAMOUT packet when the SOL stage is disabled even if the PRM says otherwise. Because of this, all primitives are sent down the pipeline for rasterization, which is wrong. If SOL is enabled, Render Stream Select is honored and primitives bound to non-zero streams are discarded after stream output. Since the only purpose of primives sent to non-zero streams is to be recorded by transform feedback, we can simply discard all geometry bound to non-zero streams then transform feedback is disabled to prevent it from ever reaching the rasterization stage. Notice that this patch introduces a small change in the behavior we get when a geometry shader emits more vertices than the maximum declared: before, a vertex that was emitted to a non-zero stream when TF was disabled would still count for the purposes of checking that we don't exceed the maximum number of output vertices declared by the shader. With this change, these vertices are completely ignored and won't increase the output vertex count, making more room for other (hopefully more useful) vertices. Fixes piglit test arb_gpu_shader5-emitstreamvertex_nodraw on Haswell and Broadwell. v2 (Ken): Drop is_haswell check in favor of doing this unconditionally. Broadwell needs the workaround as well, and it doesn't hurt to do it in general. Also tweak comments - the Haswell PRM does actually mention this ("Command Reference: Instructions" page 797). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83962 Reviewed-by: Kenneth Graunke <[email protected]> Cc: [email protected]
* i965: Add forgotten multi-stream code to Gen8 SOL state.Kenneth Graunke2015-04-061-0/+9
| | | | | | | | Fixes Piglit's arb_gpu_shader5-xfb-streams-without-invocations. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Cc: [email protected]
* i965: Fix instanced geometry shaders on Gen8+.Kenneth Graunke2015-04-061-0/+2
| | | | | | | | | | | | | Jordan added this in commit 741782b5948bb3d01d699f062a37513c2e73b076 for Gen7 platforms. I missed this when adding the Broadwell code. Fixes Piglit's spec/arb_gpu_shader5/invocation-id-{basic,in-separate-gs} with MESA_EXTENSION_OVERRIDE=GL_ARB_gpu_shader5 set. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Cc: [email protected]
* i965: Free dead GLSL IR one last time.Kenneth Graunke2015-04-061-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | While working on NIR's memory allocation model, I realized the GLSL IR memory model was broken. During glCompileShader, we allocate everything out of the _mesa_glsl_parse_state context, and reparent it to gl_shader at the end. During glLinkProgram, we allocate everything out of a temporary context, then reparent it to the exec_list containing the linked IR. But during brw_link_shader - the driver's final opportunity to do lowering and optimization - we just allocated everything out of the permanent context given to us by the linker. That memory stayed forever. Notably, passes like brw_fs_channel_expressions cause us to churn the majority of the code, so we really want to free dead IR here. Saves 125MB of memory when replaying a Dota 2 trace on Broadwell. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Implement SIMD16 texturing on Gen4.Kenneth Graunke2015-04-063-10/+90
| | | | | | | | | | | | | | | | | | | | | | | | | This allows SIMD16 mode to work for a lot more programs. Texturing is also more efficient in SIMD16 mode than SIMD8. Several messages don't actually exist in SIMD8 mode, so we did SIMD16 messages and threw away half of the data. Now we compute real data in both halves. Also, the SIMD16 "sample" message doesn't require all three coordinate components to exist (like the SIMD8 one), so we can shorten the message lengths, cutting register usage a bit. I chose to implement the visitor functionality in a separate function, since mixing true SIMD16 with SIMD8 code that uses SIMD16 fallbacks seemed like a mess. The new code bails on a few cases where we'd have to do two SIMD8 messages - we just fall back to SIMD8 for now. Improves performance in "Shadowrun: Dragonfall - Director's Cut" by about 20% on GM45 (measured with LIBGL_SHOW_FPS=1 while standing around in the first mission). v2: Add ir_txf to the has_lod case (caught by Jordan Justen). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Use SIMD16 instead of SIMD8 on Gen4 when possible.Kenneth Graunke2015-04-062-3/+4
| | | | | | | | | | | | | | | | | | | | | | | Gen5+ systems allow you to specify multiple shader programs - both SIMD8 and SIMD16 - and the hardware will automatically dispatch to the most appropriate one, given the number of subspans to be processed. However, that is not the case on Gen4. Instead, you program a single shader. If you enable multiple dispatch modes (SIMD8 and SIMD16), the shader is supposed to contain a series of jump instructions at the beginning. The hardware will launch the shader at a small offset, hitting one of the jumps. We've always thought that sounds like a pain, and weren't clear how it affected performance - is it worth having multiple shader types? So, we never bothered with SIMD16 until now. This patch takes a simpler approach: try and compile a SIMD16 shader. If possible, set the no_8 flag, telling the hardware to just use the SIMD16 variant all the time. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Respect the no_8 flag on Gen4-5.Kenneth Graunke2015-04-061-21/+34
| | | | | | | | | This flag means to ignore the SIMD8 program and only use the SIMD16 one. It was originally meant for repdata clear shaders, but I plan to use it for other things on Gen4 as well. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/fp: Set coord_components correctly for cube textures.Kenneth Graunke2015-04-061-1/+1
| | | | | | | | | | I've no idea why this was 4. It certainly seems wrong. Prevents assertion failures in fp-incomplete-tex with some upcoming patches of mine. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* nir: Remove fsin_reduced/fcos_reduced.Matt Turner2015-04-061-2/+0
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* i965/vec4: Remove emit_scs() prototype.Matt Turner2015-04-061-3/+0
| | | | | | This has never existed. Reviewed-by: Jason Ekstrand <[email protected]>
* glsl: Remove never used sin_reduced/cos_reduced.Matt Turner2015-04-063-6/+0
| | | | | | | | These were added in commit f2616e56, presumably in preparation for translating ARB vp/fp into GLSL IR. That never happened, and neither did a lowering pass that actually generated these instructions. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Make sure we always mark array surfaces as suchIago Toral Quiroga2015-04-062-2/+6
| | | | | | | | | | Even if they only have one slice, otherwise textureSize() won't produce correct results for the depth value. Fixes 10 dEQP tests in this category: dEQP-GLES3.functional.shaders.texture_functions.texturesize.sampler2darray* Reviewed-by: Mark Janes <mark.a.janes at intel.com>
* i965: Implement support for ARB_clip_control.Mathias Fröhlich2015-04-059-15/+19
| | | | | | | | | | | | | Switch between the two clip space definitions already available in hardware. Update winding order dependent state according to the clip control state. This change did not introduce new piglit quick.test regressions on an Ivybridge Mobile and a GM45 Express chipset. Also it enables and passes the clip-control and clip-control-depth-precision tests on these two chipsets. Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Mathias Froehlich <[email protected]>
* radeon: Make use of _mesa_get_viewport_xform v2.Mathias Froehlich2015-04-052-16/+18
| | | | | | | | | | | | Instead of _WindowMap just use the translation and scale of the viewport transform directly. Thereby avoid dividing by _DepthMaxF again. v2: Change order of assignments. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Mathias Froehlich <[email protected]>
* i965: Make use of _mesa_get_viewport_xform.Mathias Froehlich2015-04-054-32/+36
| | | | | | | | | Instead of _WindowMap just use the translation and scale of the viewport transform directly. Thereby avoid dividing by _DepthMaxF again. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Mathias Froehlich <[email protected]>
* i965: Use brw_nir_cubemap_normalize for NIR shadersJason Ekstrand2015-04-032-1/+5
| | | | Reviewed-by: Jordan Justen <[email protected]>
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