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* i965/vec4: Do not use DepCtrl with 64-bit instructionsIago Toral Quiroga2017-01-031-1/+13
* i965/vec4: extend the DWORD multiply DepCtrl restriction to all gen8 platformsIago Toral Quiroga2017-01-031-3/+6
* i965/vec4: don't copy propagate misaligned registersSamuel Iglesias Gonsálvez2017-01-031-0/+3
* i965/vec4: don't propagate single-precision uniforms into 4-wide instructionsIago Toral Quiroga2017-01-031-0/+11
* i965/vec4: Prevent copy propagation from violating pre-gen8 restrictionsIago Toral Quiroga2017-01-031-0/+7
* i965/vec4: prevent copy-propagation from values with a different type sizeIago Toral Quiroga2017-01-031-0/+7
* i965/vec4: don't constant propagate 64-bit immediatesConnor Abbott2017-01-031-0/+7
* i965/vec4: Fix SSBO stores for 64-bit dataIago Toral Quiroga2017-01-031-8/+32
* i965/vec4: Fix SSBO loads for 64-bit dataIago Toral Quiroga2017-01-031-4/+29
* i965/vec4: Fix UBO loads for 64-bit dataIago Toral Quiroga2017-01-031-15/+34
* i965/vec4: Add a shuffle_64bit_data helperIago Toral Quiroga2017-01-032-0/+76
* i965/vec4: support multiple dispatch widths and groups in the IR builder.Iago Toral Quiroga2017-01-031-2/+37
* i965/vec4: Lower 64-bit MADIago Toral Quiroga2017-01-032-0/+45
* i965/vec4/nir: do not emit 64-bit MADIago Toral Quiroga2017-01-031-5/+12
* i965/vec4: Skip swizzle to subnr in 3src instructions with DF operandsIago Toral Quiroga2017-01-031-1/+4
* i965/vec4: fix indentation in pack_uniform_registersIago Toral Quiroga2017-01-031-15/+15
* i965/vec4: fix pack_uniform_registers for doublesIago Toral Quiroga2017-01-031-2/+9
* i965/vec4: teach register coalescing about 64-bitIago Toral Quiroga2017-01-031-3/+19
* i965/disasm: fix subreg for dst in Align16 modeIago Toral Quiroga2017-01-031-1/+1
* i965/vec4: implement access to DF source components Z/WIago Toral Quiroga2017-01-031-0/+21
* i965/vec4: translate 64-bit swizzles to 32-bitIago Toral Quiroga2017-01-032-3/+48
* i965/vec4: add a scalarization pass for double-precision instructionsIago Toral Quiroga2017-01-032-0/+92
* i965/vec4: split double-precision SELIago Toral Quiroga2017-01-031-0/+6
* i965/vec4: teach cmod propagation about different execution sizesIago Toral Quiroga2017-01-031-1/+3
* i965/vec4: teach CSE about exec_size, group and doublesIago Toral Quiroga2017-01-031-7/+20
* i965/disasm: print NibCtrl for instructions with execsize < 8Iago Toral Quiroga2017-01-031-1/+5
* i965/vec4: dump NibCtrl for instructions with execsize != 8Iago Toral Quiroga2017-01-031-0/+3
* i965/vec4: make the generator set correct NibCtrl for SIMD4 DF instructionsIago Toral Quiroga2017-01-031-0/+9
* i965/vec4: add a SIMD lowering passIago Toral Quiroga2017-01-032-0/+161
* i965: move the group field from fs_inst to backend_instruction.Iago Toral Quiroga2017-01-033-9/+10
* i965/vec4: add a horiz_offset() helperIago Toral Quiroga2017-01-031-0/+12
* i965/vec4: handle 32 and 64 bit channels in liveness analysisJuan A. Suarez Romero2017-01-035-53/+50
* i965/vec4: dump the instruction execution sizeIago Toral Quiroga2017-01-031-1/+2
* i965/vec4: use the IR's execution sizeIago Toral Quiroga2017-01-031-0/+1
* i965/vec4: fix regs_read() for doublesIago Toral Quiroga2017-01-031-2/+2
* i965/vec4: fix size_written for doublesIago Toral Quiroga2017-01-031-1/+2
* i965: move exec_size from fs_instruction to backend_instructionIago Toral Quiroga2017-01-033-7/+8
* i965/vec4: use the new helper function to create double immediatesSamuel Iglesias Gonsálvez2017-01-031-1/+1
* i965/vec4: add a helper function to create double immediatesIago Toral Quiroga2017-01-032-0/+40
* i965/vec4: fix optimize predicate for doublesIago Toral Quiroga2017-01-031-2/+4
* i965/vec4: implement fsign() for doublesIago Toral Quiroga2017-01-031-15/+49
* i965/vec4: implement d2bIago Toral Quiroga2017-01-031-0/+18
* i965/vec4: implement d2i, d2u, i2d and u2dIago Toral Quiroga2017-01-031-0/+14
* i965/vec4: implement HW workaround for align16 double to float conversionIago Toral Quiroga2017-01-031-0/+11
* i965/vec4: add helpers for conversions to/from doublesIago Toral Quiroga2017-01-032-20/+41
* i965/vec4: Rename DF to/from F generator opcodesIago Toral Quiroga2017-01-036-20/+20
* i965/vec4: fix register allocation for 64-bit undef sourcesIago Toral Quiroga2017-01-031-1/+2
* i965/vec4: make opt_vector_float ignore doublesIago Toral Quiroga2017-01-031-0/+1
* i965/vec4: fix get_nir_dest() to use DF type for 64-bit destinationsIago Toral Quiroga2017-01-031-0/+4
* i965/vec4: fix indentation in get_nir_src()Iago Toral Quiroga2017-01-031-2/+2
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