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* i965: Add the new 3DSTATE_PS_BLEND state packet.Kenneth Graunke2014-01-315-0/+142
| | | | | | | | | | | v2: Only set GEN8_PS_BLEND_HAS_WRITEABLE_RT if color buffer writes are enabled (caught by Eric Anholt). v3: Set non-blending flags (writeable RT, alpha test, alpha to coverage) for integer formats too. +14 Piglits. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> [v2]
* i965: Replace DEPTH_STENCIL_STATE with Gen8's 3DSTATE_WM_DEPTH_STENCIL.Kenneth Graunke2014-01-315-1/+131
| | | | | | | | | | | | | | | v2: Use stencil->_WriteEnabled instead of setting GEN8_WM_DS_STENCIL_BUFFER_WRITE_ENABLE twice (suggested by Eric). v3: Mask stencil->WriteMask and stencil->ValueMask with 0xff. The field is only 8-bits, so we'd trip the new SET_FIELD assertion when core Mesa gave us a value like 0xFFFFFFFF. The Gen7 code uses structure field widths to implicitly do this truncation. Fixes Piglit tests. v4: Use uint32_t for dw1/dw2, not uint8_t. Worst. Typo. Ever. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> [v2]
* i965: Update SF, SBE, and RASTER state for Broadwell.Kenneth Graunke2014-01-315-2/+311
| | | | | | | | | | | | | | | | The attribute override portion of 3DSTATE_SBE was split out into 3DSTATE_SBE_SWIZ; various bits of 3DSTATE_SF were split out into 3DSTATE_RASTER. v2: Set Force URB Read Offset bit. Eventually the URB read offset should be set in 3DSTATE_VS, but that will require some refactoring. v3: Rebase on viewport array changes. v4: Improve comments about URB read length/offset overrides. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Bump generation assertions on workaround flushes.Kenneth Graunke2014-01-311-2/+2
| | | | | | | | I haven't investigated whether these are necessary on Broadwell or not, but for paranoia's sake, we may as well continue doing them for now. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Duplicate gen7_atoms to gen8_atoms.Kenneth Graunke2014-01-311-1/+79
| | | | | | | | It's going to diverge significantly. Starting out with a copy allows future patches to change atoms one by one. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* radeon: move driContextSetFlags(ctx) call after ctx var is initializedBrian Paul2014-01-311-2/+3
| | | | | CC: "10.0" <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r200: move driContextSetFlags(ctx) call after ctx var is initializedBrian Paul2014-01-311-2/+3
| | | | | | | Otherwise, ctx was a garbage value. CC: "10.0" <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* dri3, i915, i965: Add __DRI_IMAGE_FOURCC_SARGB8888Keith Packard2014-01-302-0/+6
| | | | | | | | | | | | | | | | The __DRIimage createImageFromFds function takes a fourcc code, but there was no fourcc code that match __DRI_IMAGE_FORMAT_SARGB8. This adds a define for that format, adds a translation in DRI3 from __DRI_IMAGE_FORMAT_SARGB8 to __DRI_IMAGE_FOURCC_SARGB8888 and then adds translations *back* to __IMAGE_FORMAT_SARGB8 in both the i915 and i965 drivers. I'll refrain from comments on whether I think having two separate sets of format defines in dri_interface.h is a good idea or not... Fixes piglit glx-tfp and glx-visuals-depth Signed-off-by: Keith Packard <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* nouveau: Use gl_constants::MinMapBufferAlignment as the alignment in ↵Siavash Eliasi2014-01-291-1/+2
| | | | | | | | | nouveau_bo_new This driver does not support GL_ARB_map_buffer_range, so no special treatment is needed for unaligned offsets in the mapping. Reviewed-by: Ian Romanick <[email protected]>
* radeon / r200: Use gl_constants::MinMapBufferAlignment as the alignment in ↵Siavash Eliasi2014-01-291-1/+1
| | | | | | | | | radeon_bo_open These drivers do not support GL_ARB_map_buffer_range, so no special treatment is needed for unaligned offsets in the mapping. Reviewed-by: Ian Romanick <[email protected]>
* i965/fs: Add a saturation propagation optimization pass.Matt Turner2014-01-284-0/+107
| | | | | | | | | | | | | | | | | | | | | | Transforms, for example, mul vgrf3, vgrf2, vgrf1 mov.sat vgrf4, vgrf3 into mul.sat vgrf3, vgrf2, vgrf1 mov vgrf4, vgrf3 which gives register_coalescing an opportunity to remove the MOV instruction. total instructions in shared programs: 1515039 -> 1504634 (-0.69%) instructions in affected programs: 798586 -> 788181 (-1.30%) GAINED: 0 LOST: 4 Reviewed-by: Jordan Justen <[email protected]>
* i965: Add can_do_saturate() method to backend_instruction.Matt Turner2014-01-282-0/+45
| | | | Reviewed-by: Jordan Justen <[email protected]>
* i965: Ignore 'centroid' interpolation qualifier in case of persample shadingAnuj Phogat2014-01-281-1/+2
| | | | | | | | | | | | I missed this change in commit f5cfb4a. It fixes the incorrect rendering caused in Dolphin Emulator. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=73915 Cc: [email protected] Signed-off-by: Anuj Phogat <[email protected]> Tested-by: Markus Wick <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* mesa: Fix Type A _INT formats to MESA_FORMAT naming standardMark Mueller2014-01-271-20/+20
| | | | | | | | | | | | | | | | | | | | | | | | | Replace Type A _INT formats names with _SINT to match naming spec, and update type C formats as follows: s/MESA_FORMAT_R_INT8\b/MESA_FORMAT_R_SINT8/g s/MESA_FORMAT_R_INT16\b/MESA_FORMAT_R_SINT16/g s/MESA_FORMAT_R_INT32\b/MESA_FORMAT_R_SINT32/g s/MESA_FORMAT_RG_INT8\b/MESA_FORMAT_RG_SINT8/g s/MESA_FORMAT_RG_INT16\b/MESA_FORMAT_RG_SINT16/g s/MESA_FORMAT_RG_INT32\b/MESA_FORMAT_RG_SINT32/g s/MESA_FORMAT_RGB_INT8\b/MESA_FORMAT_RGB_SINT8/g s/MESA_FORMAT_RGB_INT16\b/MESA_FORMAT_RGB_SINT16/g s/MESA_FORMAT_RGB_INT32\b/MESA_FORMAT_RGB_SINT32/g s/MESA_FORMAT_RGBA_INT8\b/MESA_FORMAT_RGBA_SINT8/g s/MESA_FORMAT_RGBA_INT16\b/MESA_FORMAT_RGBA_SINT16/g s/MESA_FORMAT_RGBA_INT32\b/MESA_FORMAT_RGBA_SINT32/g s/\bMESA_FORMAT_RED_RGTC1\b/MESA_FORMAT_R_RGTC1_UNORM/g s/\bMESA_FORMAT_SIGNED_RED_RGTC1\b/MESA_FORMAT_R_RGTC1_SNORM/g s/\bMESA_FORMAT_RG_RGTC2\b/MESA_FORMAT_RG_RGTC2_UNORM/g s/\bMESA_FORMAT_SIGNED_RG_RGTC2\b/MESA_FORMAT_RG_RGTC2_SNORM/g s/\bMESA_FORMAT_L_LATC1\b/MESA_FORMAT_L_LATC1_UNORM/g s/\bMESA_FORMAT_SIGNED_L_LATC1\b/MESA_FORMAT_L_LATC1_SNORM/g s/\bMESA_FORMAT_LA_LATC2\b/MESA_FORMAT_LA_LATC2_UNORM/g s/\bMESA_FORMAT_SIGNED_LA_LATC2\b/MESA_FORMAT_LA_LATC2_SNORM/g
* mesa: Fix MESA_FORMAT names containg SIGNEDMark Mueller2014-01-272-19/+19
| | | | | | | | | | | | | | | | | | | | | | | | Update comments. Replace format names containing SIGNED with SNORM appended w/decoration per the format name spec: s/MESA_FORMAT_SIGNED_R8\b/MESA_FORMAT_R_SNORM8/g s/MESA_FORMAT_SIGNED_RG88_REV\b/MESA_FORMAT_R8G8_SNORM/g s/MESA_FORMAT_SIGNED_RGBX8888\b/MESA_FORMAT_X8B8G8R8_SNORM/g s/MESA_FORMAT_SIGNED_RGBA8888\b/MESA_FORMAT_A8B8G8R8_SNORM/g s/MESA_FORMAT_SIGNED_RGBA8888_REV\b/MESA_FORMAT_R8G8B8A8_SNORM/g s/MESA_FORMAT_SIGNED_R16\b/MESA_FORMAT_R_SNORM16/g s/MESA_FORMAT_SIGNED_GR1616\b/MESA_FORMAT_R16G16_SNORM/g s/MESA_FORMAT_SIGNED_RGB_16\b/MESA_FORMAT_RGB_SNORM16/g s/MESA_FORMAT_SIGNED_RGBA_16\b/MESA_FORMAT_RGBA_SNORM16/g s/MESA_FORMAT_SIGNED_A8\b/MESA_FORMAT_A_SNORM8/g s/MESA_FORMAT_SIGNED_I8\b/MESA_FORMAT_I_SNORM8/g s/MESA_FORMAT_SIGNED_L8\b/MESA_FORMAT_L_SNORM8/g s/MESA_FORMAT_SIGNED_A16\b/MESA_FORMAT_A_SNORM16/g s/MESA_FORMAT_SIGNED_I16\b/MESA_FORMAT_I_SNORM16/g s/MESA_FORMAT_SIGNED_L16\b/MESA_FORMAT_L_SNORM16/g s/MESA_FORMAT_SIGNED_AL88\b/MESA_FORMAT_L8A8_SNORM/g s/MESA_FORMAT_SIGNED_RG88\b/MESA_FORMAT_G8R8_SNORM/g s/MESA_FORMAT_SIGNED_RG1616\b/MESA_FORMAT_G16R16_SNORM/g
* mesa: Fix MESA_FORMAT names with ALPH, INTENSITY, and LUMINANCEMark Mueller2014-01-272-43/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Compressed spelled out color components ALPHA, INTENSITY, and LUMINANCE to A, I, and L: s/MESA_FORMAT_ALPHA_UINT8\b/MESA_FORMAT_A_UINT8/g' s/MESA_FORMAT_ALPHA_UINT16\b/MESA_FORMAT_A_UINT16/g' s/MESA_FORMAT_ALPHA_UINT32\b/MESA_FORMAT_A_UINT32/g' s/MESA_FORMAT_ALPHA_INT32\b/MESA_FORMAT_A_SINT32/g' s/MESA_FORMAT_ALPHA_INT16\b/MESA_FORMAT_A_SINT16/g' s/MESA_FORMAT_ALPHA_INT8\b/MESA_FORMAT_A_SINT8/g' s/MESA_FORMAT_INTENSITY_UINT8\b/MESA_FORMAT_I_UINT8/g' s/MESA_FORMAT_INTENSITY_UINT16\b/MESA_FORMAT_I_UINT16/g' s/MESA_FORMAT_INTENSITY_UINT32\b/MESA_FORMAT_I_UINT32/g' s/MESA_FORMAT_INTENSITY_INT32\b/MESA_FORMAT_I_SINT32/g' s/MESA_FORMAT_INTENSITY_INT16\b/MESA_FORMAT_I_SINT16/g' s/MESA_FORMAT_INTENSITY_INT8\b/MESA_FORMAT_I_SINT8/g' s/MESA_FORMAT_LUMINANCE_UINT8\b/MESA_FORMAT_L_UINT8/g' s/MESA_FORMAT_LUMINANCE_UINT16\b/MESA_FORMAT_L_UINT16/g' s/MESA_FORMAT_LUMINANCE_UINT32\b/MESA_FORMAT_L_UINT32/g' s/MESA_FORMAT_LUMINANCE_INT32\b/MESA_FORMAT_L_SINT32/g' s/MESA_FORMAT_LUMINANCE_INT16\b/MESA_FORMAT_L_SINT16/g' s/MESA_FORMAT_LUMINANCE_INT8\b/MESA_FORMAT_L_SINT8/g' s/MESA_FORMAT_LUMINANCE_ALPHA_UINT8\b/MESA_FORMAT_LA_UINT8/g' s/MESA_FORMAT_LUMINANCE_ALPHA_UINT16\b/MESA_FORMAT_LA_UINT16/g' s/MESA_FORMAT_LUMINANCE_ALPHA_UINT32\b/MESA_FORMAT_LA_UINT32/g' s/MESA_FORMAT_LUMINANCE_ALPHA_INT32\b/MESA_FORMAT_LA_SINT32/g' s/MESA_FORMAT_LUMINANCE_ALPHA_INT16\b/MESA_FORMAT_LA_SINT16/g' s/MESA_FORMAT_LUMINANCE_ALPHA_INT8\b/MESA_FORMAT_LA_SINT8/g' s/MESA_FORMAT_ALPHA_FLOAT16\b/MESA_FORMAT_A_FLOAT16/g' s/MESA_FORMAT_ALPHA_FLOAT32\b/MESA_FORMAT_A_FLOAT32/g' s/MESA_FORMAT_INTESITY_FLOAT16\b/MESA_FORMAT_I_FLOAT16/g' s/MESA_FORMAT_INTESITY_FLOAT32\b/MESA_FORMAT_I_FLOAT32/g' s/MESA_FORMAT_INTENSITY_FLOAT16\b/MESA_FORMAT_I_FLOAT16/g' s/MESA_FORMAT_INTENSITY_FLOAT32\b/MESA_FORMAT_I_FLOAT32/g' s/MESA_FORMAT_LUMINANCE_FLOAT16\b/MESA_FORMAT_L_FLOAT16/g' s/MESA_FORMAT_LUMINANCE_FLOAT32\b/MESA_FORMAT_L_FLOAT32/g' s/MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16\b/MESA_FORMAT_LA_FLOAT16/g' s/MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32\b/MESA_FORMAT_LA_FLOAT32/g'
* mesa: Change many Type P MESA_FORMATs to meet naming specMark Mueller2014-01-2750-320/+320
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conversion of Type P formats as follows (w/related comment fixes): s/MESA_FORMAT_RGB565\b/MESA_FORMAT_B5G6R5_UNORM/g s/MESA_FORMAT_RGB565_REV\b/MESA_FORMAT_R5G6B5_UNORM/g s/MESA_FORMAT_ARGB4444\b/MESA_FORMAT_B4G4R4A4_UNORM/g s/MESA_FORMAT_ARGB4444_REV\b/MESA_FORMAT_A4R4G4B4_UNORM/g s/MESA_FORMAT_RGBA5551\b/MESA_FORMAT_A1B5G5R5_UNORM/g s/MESA_FORMAT_XBGR8888_SNORM\b/MESA_FORMAT_R8G8B8X8_SNORM/g s/MESA_FORMAT_XBGR8888_SRGB\b/MESA_FORMAT_R8G8B8X8_SRGB/g s/MESA_FORMAT_ARGB1555\b/MESA_FORMAT_B5G5R5A1_UNORM/g s/MESA_FORMAT_ARGB1555_REV\b/MESA_FORMAT_A1R5G5B5_UNORM/g s/MESA_FORMAT_AL44\b/MESA_FORMAT_L4A4_UNORM/g s/MESA_FORMAT_RGB332\b/MESA_FORMAT_B2G3R3_UNORM/g s/MESA_FORMAT_ARGB2101010\b/MESA_FORMAT_B10G10R10A2_UNORM/g s/MESA_FORMAT_Z24_S8\b/MESA_FORMAT_S8_UINT_Z24_UNORM/g s/MESA_FORMAT_S8_Z24\b/MESA_FORMAT_Z24_UNORM_S8_UINT/g s/MESA_FORMAT_X8_Z24\b/MESA_FORMAT_Z24_UNORM_X8_UINT/g s/MESA_FORMAT_Z24_X8\b/MESA_FORMAT_X8Z24_UNORM/g s/MESA_FORMAT_RGB9_E5_FLOAT\b/MESA_FORMAT_R9G9B9E5_FLOAT/g s/MESA_FORMAT_R11_G11_B10_FLOAT\b/MESA_FORMAT_R11G11B10_FLOAT/g s/MESA_FORMAT_Z32_FLOAT_X24S8\b/MESA_FORMAT_Z32_FLOAT_S8X24_UINT/g s/MESA_FORMAT_ABGR2101010_UINT\b/MESA_FORMAT_R10G10B10A2_UINT/g s/MESA_FORMAT_XRGB4444_UNORM\b/MESA_FORMAT_B4G4R4X4_UNORM/g s/MESA_FORMAT_XRGB1555_UNORM\b/MESA_FORMAT_B5G5R5X1_UNORM/g s/MESA_FORMAT_XRGB2101010_UNORM\b/MESA_FORMAT_B10G10R10X2_UNORM/g s/MESA_FORMAT_AL88\b/MESA_FORMAT_L8A8_UNORM/g s/MESA_FORMAT_AL88_REV\b/MESA_FORMAT_A8L8_UNORM/g s/MESA_FORMAT_AL1616\b/MESA_FORMAT_L16A16_UNORM/g s/MESA_FORMAT_AL1616_REV\b/MESA_FORMAT_A16L16_UNORM/g s/MESA_FORMAT_RG88\b/MESA_FORMAT_G8R8_UNORM/g s/MESA_FORMAT_GR88\b/MESA_FORMAT_R8G8_UNORM/g s/MESA_FORMAT_GR1616\b/MESA_FORMAT_R16G16_UNORM/g s/MESA_FORMAT_RG1616\b/MESA_FORMAT_G16R16_UNORM/g s/MESA_FORMAT_SRGBA8\b/MESA_FORMAT_A8B8G8R8_SRGB/g s/MESA_FORMAT_SARGB8\b/MESA_FORMAT_B8G8R8A8_SRGB/g s/MESA_FORMAT_SLA8\b/MESA_FORMAT_L8A8_SRGB/g Conflicts: src/mesa/drivers/dri/i965/brw_surface_formats.c src/mesa/main/format_pack.c src/mesa/main/format_unpack.c src/mesa/main/formats.c src/mesa/main/texformat.c src/mesa/main/texstore.c
* mesa: Change many Type A MESA_FORMATs to meet naming standardMark Mueller2014-01-2742-203/+203
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update comments. Conversion of the following Type A formats: s/MESA_FORMAT_RGB888\b/MESA_FORMAT_BGR_UNORM8/g s/MESA_FORMAT_BGR888\b/MESA_FORMAT_RGB_UNORM8/g s/MESA_FORMAT_A8\b/MESA_FORMAT_A_UNORM8/g s/MESA_FORMAT_A16\b/MESA_FORMAT_A_UNORM16/g s/MESA_FORMAT_L8\b/MESA_FORMAT_L_UNORM8/g s/MESA_FORMAT_L16\b/MESA_FORMAT_L_UNORM16/g s/MESA_FORMAT_I8\b/MESA_FORMAT_I_UNORM8/g s/MESA_FORMAT_I16\b/MESA_FORMAT_I_UNORM16/g s/MESA_FORMAT_R8\b/MESA_FORMAT_R_UNORM8/g s/MESA_FORMAT_R16\b/MESA_FORMAT_R_UNORM16/g s/MESA_FORMAT_Z16\b/MESA_FORMAT_Z_UNORM16/g s/MESA_FORMAT_Z32\b/MESA_FORMAT_Z_UNORM32/g s/MESA_FORMAT_S8\b/MESA_FORMAT_S_UINT8/g s/MESA_FORMAT_SRGB8\b/MESA_FORMAT_BGR_SRGB8/g s/MESA_FORMAT_RGBA_16\b/MESA_FORMAT_RGBA_UNORM16/g s/MESA_FORMAT_SL8\b/MESA_FORMAT_L_SRGB8/g s/MESA_FORMAT_Z32_FLOAT\b/MESA_FORMAT_Z_FLOAT32/g s/MESA_FORMAT_XBGR16161616_UNORM\b/MESA_FORMAT_RGBX_UNORM16/g s/MESA_FORMAT_XBGR16161616_SNORM\b/MESA_FORMAT_RGBX_SNORM16/g s/MESA_FORMAT_XBGR16161616_FLOAT\b/MESA_FORMAT_RGBX_FLOAT16/g s/MESA_FORMAT_XBGR16161616_UINT\b/MESA_FORMAT_RGBX_UINT16/g s/MESA_FORMAT_XBGR16161616_SINT\b/MESA_FORMAT_RGBX_SINT16/g s/MESA_FORMAT_XBGR32323232_FLOAT\b/MESA_FORMAT_RGBX_FLOAT32/g s/MESA_FORMAT_XBGR32323232_UINT\b/MESA_FORMAT_RGBX_UINT32/g s/MESA_FORMAT_XBGR32323232_SINT\b/MESA_FORMAT_RGBX_SINT32/g s/MESA_FORMAT_XBGR8888_UINT\b/MESA_FORMAT_RGBX_UINT8/g s/MESA_FORMAT_XBGR8888_SINT\b/MESA_FORMAT_RGBX_SINT8/g
* mesa: Rename 4 color component unsigned byte MESA_FORMATsMark Mueller2014-01-2751-215/+215
| | | | | | | | | | | | | Change all 4 color component unsigned byte formats to meet spec for P Type formats: s/MESA_FORMAT_RGBA8888\b/MESA_FORMAT_A8B8G8R8_UNORM/g s/MESA_FORMAT_RGBA8888_REV\b/MESA_FORMAT_R8G8B8A8_UNORM/g s/MESA_FORMAT_ARGB8888\b/MESA_FORMAT_B8G8R8A8_UNORM/g s/MESA_FORMAT_ARGB8888_REV\b/MESA_FORMAT_A8R8G8B8_UNORM/g s/MESA_FORMAT_RGBX8888\b/MESA_FORMAT_X8B8G8R8_UNORM/g s/MESA_FORMAT_RGBX8888_REV\b/MESA_FORMAT_R8G8B8X8_UNORM/g s/MESA_FORMAT_XRGB8888\b/MESA_FORMAT_B8G8R8X8_UNORM/g s/MESA_FORMAT_XRGB8888_REV\b/MESA_FORMAT_X8R8G8B8_UNORM/g
* mesa: change gl_format to mesa_formatMark Mueller2014-01-2764-191/+191
| | | | s/\bgl_format\b/mesa_format/g. Use better name for Mesa Formats enum
* mesa: GL_EXT_framebuffer_blit is not optionalIan Romanick2014-01-275-5/+0
| | | | | | | | | Every driver supports it. All current and future Gallium drivers always support it, and all existing classic drivers support it. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* radeon: Enable GL_EXT_framebuffer_blitIan Romanick2014-01-271-0/+1
| | | | | | | | | | | | | | | | The dd_function_table::BlitFramebuffer is already initialized to _mesa_meta_BlitFramebuffer, so it should just work. Tested on a Radeon 7500 (OpenGL renderer string: Mesa DRI R100 (RV200 5157) TCL DRI2). I couldn't do a full piglit run because it would tank the system with or without this patch. I just ran all the blit tests (-t blit to piglit-run.py). Only fbo-sys-sub-blit failed. All of the other tests that weren't skipped (i.e., all the multisample and sRGB tests skip) passed. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* r200: Enable GL_EXT_framebuffer_blitIan Romanick2014-01-271-0/+1
| | | | | | | | | | | | The dd_function_table::BlitFramebuffer is already initialized to _mesa_meta_BlitFramebuffer, so it should just work. Tested on a FireGL 8800 (OpenGL renderer string: Mesa DRI R200 (R200 5148) TCL DRI). Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* radeon / r200: Pass the API into _mesa_initialize_contextIan Romanick2014-01-274-3/+5
| | | | | | | | | | Otherwise an application that requested an OpenGL ES 1.x context would actually get a desktop OpenGL context. Signed-off-by: Ian Romanick <[email protected]> Cc: "9.1 9.2 10.0" <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Don't store qpitch / 4 as mt->qpitch for compressed surfaces.Kenneth Graunke2014-01-252-5/+8
| | | | | | | | | | | | | | | | | | | | Broadwell requires software to specify QPitch in a bunch of packets, so we decided to store it in the miptree. However, when I did that refactoring, I missed a subtlety: the hardware expects QPitch to be "in units of rows in the uncompressed surface". This is the value we originally compute. However, for compressed surfaces, we then divided it by 4 (the block height), to obtain the physical layout. This is no longer the QPitch Broadwell expects. So, store the original undivided value in mt->qpitch, but continue to use the divided value in brw_miptree_layout_texture_array(). For non-Broadwell platforms, this should have no impact at all. Helps fix Piglit's "getteximage-targets S3TC CUBE" test on Broadwell. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* Update .gitignore for Catalan translations build artifactsPaul Berry2014-01-241-0/+1
| | | | | | Causes git to ignore the new build artifacts introduced by commit d5e5367e8992c2e5322d35fba8d86c33a0db6825 (driconf: Add Catalan translations).
* i965/gen7: Use to the correct program when uploading transform feedback state.Paul Berry2014-01-232-10/+6
| | | | | | | | | | | | Transform feedback may come from either the geometry shader or the vertex shader, so we can't use ctx->Shader.CurrentProgram[MESA_SHADER_VERTEX] to find the current post-link transform feedback information. Fortunately we can use ctx->TransformFeedback.CurrentObject->shader_program. Cc: 10.0 <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Remove *_generator::shader field; use prog field instead.Paul Berry2014-01-237-18/+8
| | | | | | | | | | | | | | | The "shader" field in fs_generator, vec4_generator, and gen8_generator was only used for one purpose; to figure out if we were compiling an assembly program or a GLSL shader (shader is NULL for assembly programs). And it wasn't being used properly: in vec4 shaders we were always initializing it based on prog->_LinkedShaders[MESA_SHADER_FRAGMENT], regardless of whether we were compiling a geometry shader or a vertex shader. This patch simplifies things by using the "prog" field instead; this is also NULL for assembly programs. Reviewed-by: Kenneth Graunke <[email protected]>
* driconf: Add Catalan translationsAlex Henrie2014-01-232-1/+322
| | | | | | See the instructions in Makefile.am under "Adding new translations". Reviewed-by: Eric Anholt <[email protected]>
* driconf: Correct and update Spanish translationsAlex Henrie2014-01-231-31/+33
| | | | Reviewed-by: Eric Anholt <[email protected]>
* driconf: Synchronize po filesAlex Henrie2014-01-235-357/+702
| | | | | | | See the instructions in Makefile.am under "Updating existing translations". Reviewed-by: Eric Anholt <[email protected]>
* radeon / r200: Eliminate BEGIN_BATCH_NO_AUTOSTATEIan Romanick2014-01-2311-32/+27
| | | | | | | | | | | | | | Sed job: grep -lr BEGIN_BATCH_NO_AUTOSTATE src/mesa/drivers/dri/ | while read f do cat $f | sed 's/BEGIN_BATCH_NO_AUTOSTATE/BEGIN_BATCH/g' > x mv x $f done Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Cc: Marek Olšák <[email protected]>
* radeon / r200: Remove unused 'dostate' parameterIan Romanick2014-01-232-4/+2
| | | | | | | | | | | | | | This parameter hasn't been used since January 2010 (commit 29e02c7). Fixes the following warning in both radeon and r200: radeon_common.c: In function 'r200_rcommonBeginBatch': radeon_common.c:762:14: warning: unused parameter 'dostate' [-Wunused-parameter] Note that now BEGIN_BATCH and BEGIN_PATCH_NO_AUTOSTATE are identical. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Cc: Marek Olšák <[email protected]>
* radeon / r200: Fix 'empty body' warningIan Romanick2014-01-231-2/+2
| | | | | | | | | radeon_common.c: In function 'radeon_draw_buffer': radeon_common.c:237:3: warning: suggest braces around empty body in an 'if' statement [-Wempty-body] Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Cc: Marek Olšák <[email protected]>
* radeon / r200: Fix incompatible pointer type warningIan Romanick2014-01-231-2/+1
| | | | | | | | | | | | | | | | | When parameters were removed from dd_function_table::Viewport (commit 065bd6ff), radeon_viewport (in both radeon and r200) started generating a warning. radeon_common.c: In function 'r200_radeon_viewport': radeon_common.c:415:15: warning: assignment from incompatible pointer type [enabled by default] radeon_common.c:419:23: warning: assignment from incompatible pointer type [enabled by default] I didn't notice this initially, and it's harmless because the function is never called through the incorrectly typed pointer. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Cc: Marek Olšák <[email protected]>
* i965/blorp: switch eu-emitter to use FS IR and fs_generatorTopi Pohjolainen2014-01-233-120/+84
| | | | | | | | | | | | | | | | | | No regressions on IVB (piglit quick + unit tests). v2 (Paul): - no need to patch the unit tests anymore. Original logic was altered and unit tests updated to match the fs-generator - lrp emission moves from the blorp compiler core into the emitter here (previously there was a separate refactoring patch which is not really needed anymore as the lrp logic got refactored when the original lrp logic got fixed). - pass 'BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX' to the generator in fs_inst::target instead of hardcoding it Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/fs: add support for BRW_OPCODE_AVG in fs_generatorTopi Pohjolainen2014-01-231-0/+3
| | | | | | | Needed for compiling blorp blit programs. Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/fs: introduce blorp specific rt-write for fs_generatorTopi Pohjolainen2014-01-234-0/+23
| | | | | | | | | | | | | | | | | The compiler for blorp programs likes to emit instructions for the message construction itself meaning that the generator needs to skip any such when blorp programs are translated for the hw. In addition, the binding table control is special for blorp programs and the generator does not need to update the binding tables associated with the compiler bookkeeping (this in fact gets thrown away as the blorp compiler sets the program data in its own way). v2 (Paul): do not hardcode the binding table index but use fs_inst::target instead. Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/fs: allow unit tests to dump the final patched assemblyTopi Pohjolainen2014-01-232-8/+10
| | | | | | | | | | | | | | Unit tests comparing generated blorp programs to known good need to have the dump in designated file instead of in default standard output. The comparison also expects the jump counters of if-else-instructions to be correctly set and hence the dump needs to be taken _after_ 'patch_IF_ELSE()' is run (the default dump of the fs_generator does this before). v2 (Paul): dropped the redundant 'dump_enabled' argument Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/blorp: wrap brw_IF/ELSE/ENDIF() into eu-emitterTopi Pohjolainen2014-01-232-9/+23
| | | | | | | v2 (Paul): renamed emit_if() to emit_cmp_if() Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/blorp: wrap RNDD (/brw_RNDD(&func, /emit_rndd(/)Topi Pohjolainen2014-01-232-2/+8
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/blorp: wrap FRC (/brw_FRC(&func, /emit_frc(/)Topi Pohjolainen2014-01-232-4/+10
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/blorp: wrap MUL (/brw_MUL(&func, /emit_mul(/)Topi Pohjolainen2014-01-232-9/+16
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/blorp: wrap OR (/brw_OR(&func, /emit_or(/)Topi Pohjolainen2014-01-232-24/+31
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/blorp: wrap SHL (/brw_SHL(&func, /emit_shl(/)Topi Pohjolainen2014-01-232-12/+19
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/blorp: wrap SHR (/brw_SHR(&func, /emit_shr(/)Topi Pohjolainen2014-01-232-12/+19
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/blorp: wrap ADD (/brw_ADD(&func, /emit_add(/)Topi Pohjolainen2014-01-232-18/+32
| | | | | | | | In addition, the special case requiring explicit execution size control is wrapped manually. Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/blorp: wrap AND (/brw_AND(&func, /emit_and(/)Topi Pohjolainen2014-01-232-39/+46
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/blorp: wrap MOV (/brw_MOV(&func, /emit_mov(/)Topi Pohjolainen2014-01-232-35/+45
| | | | | | | | In addition, the two special cases requiring explicit execution size control are wrapped manually. Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/blorp: wrap emission of if-equal-assignmentTopi Pohjolainen2014-01-232-24/+12
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-22 20:55:02 +0000