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* i965: Drop batch_size argument from brw_bufmgr_init().Kenneth Graunke2017-09-013-4/+3
| | | | | | This is dead code and hasn't been used in a long time. Reviewed-by: Chris Wilson <[email protected]>
* i965: Rename brw_bo::offset64 to gtt_offset.Chris Wilson2017-09-013-12/+35
| | | | | | | | | | | | | | | | | We can drop the meaningless "64" suffix - libdrm_intel originally had an "offset" field that was an "unsigned long" which was the wrong size, and we couldn't remove/alter that field without breaking ABI, so we had to add a uint64_t "offset64" field. "gtt_offset" is also more descriptive than "offset". (Patch originally written by Ken, but Chris suggested a better name and supplied the giant comment making up the bulk of the patch, so I changed the authorship to him.) Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Wilson <[email protected]>
* i965: Drop the BRW_BATCH_STRUCT macro.Kenneth Graunke2017-09-012-4/+1
| | | | | | | It's used in exactly one place these days, and not much simpler than just calling intel_batchbuffer_data directly. Reviewed-by: Chris Wilson <[email protected]>
* i965: Don't double count the batch in aperture_space.Kenneth Graunke2017-09-011-1/+1
| | | | | | | | | intel_batchbuffer_reset calls add_exec_bo on the batch right away, which adds in the batch BO size. Fixes: 29ba502a4e28 ("i965: Use I915_EXEC_BATCH_FIRST when available.") Reviewed-by: Chris Wilson <[email protected]>
* i965: Use BLORP for buffer object stall avoidance blits instead of BLT.Kenneth Graunke2017-08-301-11/+11
| | | | | | | | Improves performance of GFXBench4 tests at 1024x768 on a Kabylake GT2: - Manhattan 3.1 by 1.32134% +/- 0.322734% (n=8). - Car Chase by 1.25607% +/- 0.291262% (n=5). Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Always flush caches after blitting to a GL buffer object.Kenneth Graunke2017-08-301-1/+3
| | | | | | | | | | | | | | | | | When we blit data into a buffer object, we may need to invalidate any caches that might contain stale data, so the new data becomes visible. For example, if the buffer object is bound as a vertex buffer, we need to invalidate the vertex fetch cache. While this flushing was missing, it usually happened implicitly for non-obvious reasons: we're usually on the render ring, and calling intel_emit_linear_blit() would require switching to the BLT ring, causing an implicit flush. This likely provoked the kernel to do PIPE_CONTROLs on our behalf. Although, Gen4-5 wouldn't have this behavior. At any rate, we should do it ourselves. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Add PIPE_CONTRTOL_DATA_CACHE flush to brw_emit_mi_flush().Kenneth Graunke2017-08-301-0/+1
| | | | | | | | | Although we're phasing out brw_emit_mi_flush(), we still use it in some places in order to "flush everything". In a number of those places, we write data to a buffer that we may then bind as an image surface, SSBO, or atomic buffer. Those usages require us to flush the data cache. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Add a brw_blorp_copy_buffers() command.Kenneth Graunke2017-08-302-0/+29
| | | | | | | | This exposes the new blorp_copy_buffer() functionality to i965. It should be a drop-in replacement for intel_emit_linear_blit() (other than the arguments being backwards, for consistency with BLORP). Reviewed-by: Jason Ekstrand <[email protected]>
* i965: drop unused brw->needs_unlit_centroid_workaroundLionel Landwerlin2017-08-302-11/+0
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965: drop brw->has_surface_tile_offset in favor of devinfo'sLionel Landwerlin2017-08-305-8/+9
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965: drop unused brw->no_simd8Lionel Landwerlin2017-08-301-1/+0
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965: drop unused brw->has_plnLionel Landwerlin2017-08-302-2/+0
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965: drop brw->must_use_separate_stencil in favor of devinfo'sLionel Landwerlin2017-08-304-4/+5
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965: drop unused brw->has_negative_rhw_bugLionel Landwerlin2017-08-302-2/+0
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965: drop unused brw->has_compr4Lionel Landwerlin2017-08-302-2/+0
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965: drop brw->has_llc in favor of devinfo->has_llcLionel Landwerlin2017-08-307-8/+8
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965: drop brw->is_broxtonLionel Landwerlin2017-08-304-5/+2
| | | | | | | | | We need to take some take here as brw->is_broxton has been used to check whether the device is a low power gen9 (aka Atom gen9 platform). Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965: drop brw->is_cherryview in favor of devinfo->is_cherryviewLionel Landwerlin2017-08-303-4/+4
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965: drop brw->is_haswell in favor of devinfo->is_haswellLionel Landwerlin2017-08-3023-44/+45
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965: drop brw->is_baytrail in favor of devinfo->is_baytrailLionel Landwerlin2017-08-308-13/+13
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965: drop brw->is_g4x in favor of devinfo->is_g4xLionel Landwerlin2017-08-308-12/+10
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965: drop brw->gt in favor of devinfo->gtLionel Landwerlin2017-08-305-8/+5
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965: drop brw->gen in favor of devinfo->genLionel Landwerlin2017-08-3047-311/+506
| | | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* i965: add 2xMSAA 16xMSAA modes to DRI configs.Kevin Rogovin2017-08-301-5/+18
| | | | | | | | | | | For Gen8, add 2xMSAA. For Gen9, add 2xMSAA and 16xMSAA. Special thanks to Eero Tamminen for reporting rasterizer numbers being twice what it should be for 2xMSAA under a benchmark. V2: Make pointer name less ugly + add 2xMSAA for Gen8 Reviewed-by: Kenneth Graunke <[email protected]>
* Revert "i965: add 2xMSAA and 16xMSAA to DRI configs for Gen9."Kenneth Graunke2017-08-301-10/+3
| | | | | | | | | This reverts commit f6d38785e8b28a6dd303884798b823e289817741. Kevin's original patch accidentally didn't add 2x for Gen8; he sent a v2 with a bunch of style fixes shortly after I pushed the original patch, not knowing it was coming. Let's just revert this one, apply v2, and move on.
* i965: Bump the initial program cache size from 4kB to 16kB.Kenneth Graunke2017-08-291-1/+1
| | | | | | | | | | | | | | | | Our initial size of 4kB is way too small to do anything useful, so we end up growing it at least a few times. We may as well start it larger. Some data points: - Dinoshade (from Mesa Demos): hit 8kB. - Chromium 60: hit 16kB after browsing a few things in Google Docs. - GFXBench4 TRex/Manhattan 3.1: hit 128kB - Unigine Valley 1.0: hit 512kB It might make sense to start it even larger. Acked-by: Matt Turner <[email protected]>
* i965: Issue performance warnings when growing the program cacheKenneth Graunke2017-08-291-0/+3
| | | | | | | This involves a bunch of unnecessary copying, a batch flush, and state re-emission. Reviewed-by: Matt Turner <[email protected]>
* i965: add 2xMSAA and 16xMSAA to DRI configs for Gen9.Kevin Rogovin2017-08-291-3/+10
| | | | | | | | | Special thanks to Eero Tamminen for reporting rasterizer numbers being twice what it should be for 2xMSAA under a benchmark. Signed-off-by: Kevin Rogovin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add $(WNO_OVERRIDE_INIT) to AM_CFLAGSMatt Turner2017-08-291-0/+1
| | | | | | | | brw_surface_formats.c and genX_blorp_exec.c do this a lot, causing lots of warnings from clang. Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* i965: Mark functions used conditionally as UNUSEDMatt Turner2017-08-292-3/+3
| | | | | | | | The functions we're marking as UNUSED in genX_state_upload.c are used only when compiling for particular generations. Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* i965: Explicitly cast between different enumsMatt Turner2017-08-291-4/+4
| | | | | | | | | | | | | Fixes warnings like warning: implicit conversion from enumeration type 'enum isl_format' to different enumeration type 'enum GEN10_SURFACE_FORMAT' [-Wenum-conversion] .SourceElementFormat = ISL_FORMAT_R32_UINT, ^~~~~~~~~~~~~~~~~~~ Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* i965: Remove some 'inline' keywordsMatt Turner2017-08-291-7/+7
| | | | | | | | | brw_texture_view_sane() is only used by an assert()... No difference in the resulting binary with gcc-6.3.0 or clang-4.0. Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* i965: Fix whitespace issues in intel_buffer_objects.c.Kenneth Graunke2017-08-281-31/+29
| | | | Convert tabs to spaces and rewrap one long line.
* i965: Use GEN_GEN and GEN_IS_HASWELL in genX_state_upload.c code.Kenneth Graunke2017-08-251-4/+4
| | | | | | | | We were using brw->gen, brw->is_haswell, and devinfo->gen in a few places, when we could just use GEN_GEN and GEN_IS_HASWELL, which are evaluated at compile time. Reviewed-by: Eduardo Lima Mitev <[email protected]>
* mesa: Implement GL_ARB_polygon_offset_clampAdam Jackson2017-08-251-1/+1
| | | | | | | | | | | Semantically identical to the EXT version (whose string is still valid for GLES), so rename the bit but expose both extension strings. (Suggested by Ilia Mirkin and Ian Romanick.) v3: Fix the entrypoint alias in GL4x.xml (Ilia) Signed-off-by: Adam Jackson <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* mesa: Implement GL_ARB_texture_filter_anisotropicAdam Jackson2017-08-253-0/+3
| | | | | | | | | | | The only difference from the EXT version is bumping the minmax to 16, so just hit all the drivers at once. v2: Fix driver names, add to 17.3 release notes (Ilia Mirkin) Reviewed-by: Ilia Mirkin <[email protected]> Signed-off-by: Adam Jackson <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: add missing `const` in function signatureEric Engestrom2017-08-241-1/+1
| | | | | | | | | | | | | Gets rid of a few warnings of the form: src/mesa/drivers/dri/i965/intel_screen.c:918:49: warning: passing argument 2 of ‘modifier_is_supported’ discards ‘const’ qualifier from pointer target type [-Wdiscarded-qualifiers] !modifier_is_supported(&screen->devinfo, f, 0, modifier)) ^ src/mesa/drivers/dri/i965/intel_screen.c:301:1: note: expected ‘struct intel_image_format *’ but argument is of type ‘const struct intel_image_format *’ Fixes: 1efd73df39b39589d26f "i965: Advertise the CCS modifier" Cc: Ben Widawsky <[email protected]> Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Stop using wm_prog_data->binding_table.render_target_start.Kenneth Graunke2017-08-231-7/+3
| | | | | | | | | | | | | Render target surfaces always start at binding table index 0. This is required for us to use headerless FB writes, which we really want to do. So, we'll never change that. Given that, it's not necessary to look up a wm_prog_data field which we already know contains 0. We can drop the dependency in brw_renderbuffer_surfaces (Gen4-5)...which was already confusingly missing from gen6_renderbuffer_surfaces. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Add a brw_wm_prog_data::has_render_target_reads field.Kenneth Graunke2017-08-231-4/+2
| | | | | | | State upload code should use prog_data rather than poking at shader_info directly. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Inline brw_update_renderbuffer_surfaces().Kenneth Graunke2017-08-232-38/+20
| | | | | | Less baklava layers. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Pass fb into emit_null_surface instead of dimensions.Kenneth Graunke2017-08-231-16/+12
| | | | | | | We either want the framebuffer dimensions or 1x1x1. Passing fb and falling back to 1x1x1 lets us shorten some calls. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Devirtualize update_renderbuffer_surface.Kenneth Graunke2017-08-234-30/+5
| | | | | | Replace piles of my own boilerplate with 1-2 lines of code. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Delete update_renderbuffer_surface flags.Kenneth Graunke2017-08-232-21/+5
| | | | | | | | | We don't need yet another set of flags. The function already has access to both brw and the unit, so it can check brw->draw_aux_buffer_disabled itself in one line of code. The layered flag was only used to assert that Gen4-5 doesn't do layered rendering, which isn't that useful. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Make brw_update_renderbuffer_surface static.Kenneth Graunke2017-08-232-11/+6
| | | | | | | | Also rename it to gen6_update_renderbuffer_surface, as this is the function for Gen6+. Having functions named "brw_*" and "gen4_*" is confusing...if we're using gens, let's stick with those. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Drop BRW_NEW_BLORP from SURFACE_STATE setup code.Kenneth Graunke2017-08-235-29/+1
| | | | | | | BLORP invalidates the binding tables, but it doesn't destroy any of the existing SURFACE_STATE entries in the statebuffer. We can reuse those. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Make a BRW_NEW_FAST_CLEAR_COLOR dirty bit.Kenneth Graunke2017-08-238-5/+25
| | | | | | | | | | | | | | | | | | | When changing fast clear colors, we need to emit new SURFACE_STATE with the updated color at the next draw call. Most things work today because the atoms that handle SURFACE_STATE for images (mutable images, textures, render targets) also listen to BRW_NEW_BLORP, causing us to re-emit these on every BLORP operation. However, this is overkill - most BLORP operations don't require us to re-emit SURFACE_STATE. One case where this is broken today is a fast clear to a different color followed by a non-coherent framebuffer fetch. The renderbuffer read atom doesn't listen to BRW_NEW_BLORP, and would not get the new fast clear color. Cc: [email protected] Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Drop Gen7+ nonsense from brw_ff_gs.c.Kenneth Graunke2017-08-231-4/+3
| | | | | | | | | | brw_ff_gs.c is about using the geometry shader to implement things that the fixed function ought to do, but doesn't on old hardware. Gen7+ does not need this. We should drop the misleading comment about Gen7 not using geometry shaders. Reviewed-by: Timothy Arceri <[email protected]>
* i965: Only set key->flat_shade if COL0/COL1 are written.Kenneth Graunke2017-08-231-1/+3
| | | | | | This may reduce some recompiles. Reviewed-by: Timothy Arceri <[email protected]>
* i965: Clean up brwNewProgram().Kenneth Graunke2017-08-231-28/+5
| | | | | | | | | | All shader stages do the exact same thing, so we don't need the switch statement, or the redundant FS case. I believe these used to be different before Tim eliminated the (e.g.) brw_vertex_program subclasses. Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* i965/clear: Quantize the depth clear value based on the formatJason Ekstrand2017-08-211-2/+12
| | | | | | | | | | | | | | | | | | In f9fd976e8adba733b08d we changed the clear value to be stored as an isl_color_value. This had the side-effect same clear value check is now happening directly between the f32[0] field of the isl_color_value and ctx->Depth.Clear. This isn't what we want for two reasons. One is that the comparison happens in floating point even for Z16 and Z24 formats. Worse than that, ctx->Depth.Clear is a double so, even for 32-bit float formats, we were comparing as doubles and not floats. This means that the test basically always fails for anything other than 0.0f and 1.0f. This caused a slight performance regression in Lightsmark 2008 because it was using a depth clear value of 0.999 which can't be stored in a 32-bit float so we were doing unneeded resolves. Reviewed-by: Kenneth Graunke <[email protected]> Bugzilla: https://bugs.freedesktop.org/101678 Cc: "17.2" <[email protected]>
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