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* i965: Use nir_lower_load_const_to_scalar().Kenneth Graunke2016-02-081-0/+4
* i965: Don't add barrier deps for FB write messages.Kenneth Graunke2016-02-081-3/+4
* i965: Rename define for the PIPE_CONTROL DC flush bit.Francisco Jerez2016-02-085-6/+6
* i965: Invalidate state cache before L3 partitioning set-up.Francisco Jerez2016-02-081-0/+1
* i965: Fix cache pollution race during L3 partitioning set-up.Francisco Jerez2016-02-081-8/+23
* i965/fs: Don't emit unnecessary SEL instruction from emit_image_atomic().Francisco Jerez2016-02-081-1/+1
* i965/vec4: Update vec4 unit tests for commit 01dacc83ff.Matt Turner2016-02-083-10/+24
* dri/common: include debug_output.h to silence warningBrian Paul2016-02-081-0/+1
* i965/vec4: don't copy ATTR into 3src instructions with complex swizzlesMatt Turner2016-02-051-4/+10
* main: Use a derived value for the default sample countNeil Roberts2016-02-051-0/+19
* DRI_CONFIG: Add option to override vendor idPatrick Rudolph2016-02-041-0/+5
* i965/fs: Allocate single register at a time for constants.Matt Turner2016-02-041-3/+3
* i965/gen8: Initialize aux_mode to GEN8_SURFACE_AUX_MODE_NONEJordan Justen2016-02-021-2/+2
* Revert "i965: Provide sse2 version for rgba8 <-> bgra8 swizzle"Roland Scheidegger2016-02-022-62/+12
* i965: Provide sse2 version for rgba8 <-> bgra8 swizzleRoland Scheidegger2016-02-022-12/+62
* i965/gen7+: Use NIR for lowering of pack/unpack opcodes.Matt Turner2016-02-013-19/+29
* i965/vec4: Implement nir_op_pack_uvec2_to_uint.Matt Turner2016-02-011-0/+18
* i965/fs: Implement support for extract_word.Matt Turner2016-02-015-0/+56
* glsl: Remove 2x16 half-precision pack/unpack opcodes.Matt Turner2016-02-011-3/+0
* i965/fs: Switch from GLSL IR to NIR for un/packHalf2x16 scalarizing.Matt Turner2016-02-013-11/+7
* i965: Make separate nir_options for scalar/vector stages.Matt Turner2016-02-011-28/+33
* i965: Move brw_compiler_create() to new brw_compiler.c.Matt Turner2016-02-015-133/+161
* i965/skl: Utilize new 5th bit for gateway messagesBen Widawsky2016-01-271-2/+4
* glsl: move to compiler/Emil Velikov2016-01-2615-19/+19
* nir: move to compiler/Emil Velikov2016-01-267-9/+8
* nir: move glsl_types.{cpp,h} to compilerEmil Velikov2016-01-266-6/+6
* nir: move shader_enums.[ch] to compilerEmil Velikov2016-01-261-0/+1
* i965/bxt: Fix conservative wm thread counts.Ben Widawsky2016-01-251-1/+1
* meta: Use internal functions to set texture parametersIan Romanick2016-01-254-24/+49
* meta/blit: Restore GL_DEPTH_STENCIL_TEXTURE_MODE state for GL_TEXTURE_RECTANGLEIan Romanick2016-01-251-8/+8
* meta/copy_image: Fix typo in commentIan Romanick2016-01-251-1/+1
* i965: Implement a drirc workaround for broken dual color blending.Kenneth Graunke2016-01-228-9/+28
* i965/fs: Remove unused count from vs urb setupBen Widawsky2016-01-221-6/+0
* i915: correctly parse/set the context flagsEmil Velikov2016-01-221-0/+2
* i965/vec4/tcs: Return NULL instead of false in brw_compile_tcs()Eduardo Lima Mitev2016-01-211-1/+1
* i965: Implement compute sampler state atom.Francisco Jerez2016-01-194-1/+24
* i965: Trigger CS state reemission when new sampler state is uploaded.Francisco Jerez2016-01-192-1/+2
* i965/vec4: Spaces around operators.Matt Turner2016-01-191-1/+1
* i965: Inform compiler of variable range to silence warning.Matt Turner2016-01-191-1/+2
* i965: adding missing headers to the dist tarballEmil Velikov2016-01-181-0/+2
* i965/fs: Always set channel 2 of texture headers in some stagesJason Ekstrand2016-01-151-0/+8
* i965/fs/generator: Take an actual shader stage rather than a stringJason Ekstrand2016-01-157-11/+14
* i965/vec4: Use UW type for multiply into accumulator on GEN8+Jason Ekstrand2016-01-151-1/+5
* i965: Apply add_const_offset_to_base for vec4 VS inputs too.Kenneth Graunke2016-01-141-5/+5
* i965: Make add_const_offset_to_base() work at the shader level.Kenneth Graunke2016-01-141-17/+21
* i965: Make an is_scalar boolean in brw_compile_vs().Kenneth Graunke2016-01-141-5/+5
* i965/gen7.5+: Disable resource streamer during GPGPU workloads.Francisco Jerez2016-01-143-1/+42
* i965/gen7: Emit stall and dummy primitive draw after switching to the 3D pipe...Francisco Jerez2016-01-141-0/+24
* i965/gen4-5: Emit MI_FLUSH as required prior to switching pipelines.Francisco Jerez2016-01-141-0/+13
* i965/gen6-7: Implement stall and flushes required prior to switching pipelines.Francisco Jerez2016-01-141-0/+37
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