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* intel: Stop creating the wrapped depth irb.Eric Anholt2011-12-192-111/+8
* i965: Properly demote the depth mt format for fake packed depth/stencil.Eric Anholt2011-12-194-3/+19
* intel: Reuse intel_miptree_match_image().Eric Anholt2011-12-191-9/+6
* intel: Stop creating the wrapped stencil irb.Eric Anholt2011-12-195-78/+67
* osmesa: fix RGB565 renderingAlex Galakhov2011-12-191-0/+4
* i965/vs: Add a new dst_reg constructor for file, number, type, and mask.Kenneth Graunke2011-12-181-0/+10
* i965/vs: Add vec4_instruction::is_tex() query.Kenneth Graunke2011-12-182-0/+11
* i965: Rename texturing ops from FS_OPCODE to SHADER_OPCODE, except TXB.Kenneth Graunke2011-12-185-46/+48
* i965/fs: Don't swizzle the results of textureSize().Kenneth Graunke2011-12-181-0/+3
* meta: use _mesa_prepare_mipmap_level() in the mipmap generation codeBrian Paul2011-12-161-35/+12
* mesa: implement DrawTransformFeedback from ARB_transform_feedback2Marek Olšák2011-12-153-7/+14
* i965: Drop separate stencil assertions in update_draw_buffer().Eric Anholt2011-12-141-16/+0
* intel: Simplify and touch up the FBO completeness test.Eric Anholt2011-12-141-18/+21
* intel: Remove another renderbuffer allocation path.Eric Anholt2011-12-141-8/+4
* intel: Make the separate stencil RB storage path match texture more.Eric Anholt2011-12-141-76/+52
* intel: Move S8 width/height alignment to miptree creation.Eric Anholt2011-12-143-55/+22
* intel: Drop check for wrapped_depth in RB mapping.Eric Anholt2011-12-141-1/+1
* intel: Fix uninitialized values in debug output for renderbuffer mapping.Eric Anholt2011-12-141-1/+1
* radeon: stop using _DepthBuffer, _StencilBuffer fieldsBrian Paul2011-12-132-9/+8
* nouveau: stop using _DepthBuffer, _StencilBuffer fieldsBrian Paul2011-12-136-13/+14
* mesa,intel: use _mesa_image_offset() for PBOsnobled2011-12-081-2/+3
* mesa/drivers: use new swrast renderbuffer functionsBrian Paul2011-12-0812-62/+74
* mesa: rewrite accum buffer supportBrian Paul2011-12-082-2/+3
* mesa: remove the ctx->Driver.IsTextureResident() hookBrian Paul2011-12-081-1/+0
* mesa: remove TextureMemCpy driver hookBrian Paul2011-12-081-1/+0
* i965 gen6: Implement pass-through GS for transform feedback.Paul Berry2011-12-076-46/+208
* i965: Clean up misleading defines for DWORD 2 of URB_WRITE header.Paul Berry2011-12-075-24/+59
* i965 gs: Clean up dodgy register re-use, at the cost of a few MOVs.Paul Berry2011-12-072-65/+111
* i965 gen6: Allocate URB space for GSPaul Berry2011-12-073-12/+63
* i965: Set the maximum number of GS URB entries on Sandybridge.Kenneth Graunke2011-12-071-0/+2
* i965: Only convert if/else to conditional adds prior to Gen6.Paul Berry2011-12-071-2/+28
* i965 gs: Remove unnecessary mapping of key->primitive.Paul Berry2011-12-072-16/+7
* i965: Set Ivybridge's is_array SURFACE_STATE bit.Kenneth Graunke2011-12-071-1/+2
* i965: Return BRW_DEPTHBUFFER_D32_FLOAT as the null-depthbuffer format.Kenneth Graunke2011-12-071-0/+3
* intel: Update comment about how depth/stencil miptrees are handled.Eric Anholt2011-12-071-6/+18
* intel: Rely on miptree mapping for all renderbuffer maps.Eric Anholt2011-12-072-202/+21
* intel: Add support for LLC-cached reads of X-tiled miptrees using a blit.Eric Anholt2011-12-072-0/+83
* intel: Handle MapRenderbuffer of fake packed depth/stencil using miptree maps.Eric Anholt2011-12-071-138/+2
* intel: Track miptrees for fake packed depth/stencil renderbuffers.Eric Anholt2011-12-071-0/+10
* intel: Make the fake packed depth/stencil mappings use a cached temporary.Eric Anholt2011-12-072-121/+129
* intel: Make intel_region_map return void *.Eric Anholt2011-12-072-4/+4
* intel: Move separate-stencil s8 mapping logic to intel_miptree_map.Eric Anholt2011-12-072-113/+112
* intel: Move the gtt-particular texture mapping logic to a helper function.Eric Anholt2011-12-071-49/+71
* intel: Make mapping of texture slices track the region of interest.Eric Anholt2011-12-072-5/+51
* intel: Move the teximage mapping logic to a miptree level/slice mapping.Eric Anholt2011-12-073-48/+109
* intel: Only prefer separate stencil when we can do HiZ.Eric Anholt2011-12-072-4/+14
* i965: Set SURFACE_STATE vertical alignment bit on Ivybridge.Kenneth Graunke2011-12-061-0/+7
* radeon: add original r100 to the always tiled depth list.Dave Airlie2011-12-061-1/+1
* osmesa: remove unused bpc variableFabio Pedretti2011-12-061-8/+0
* radeon/r200: add RV200 detiling + add an always tiled flagDave Airlie2011-12-063-37/+72
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